Transistor epitaxial wafer and transistor produced by using same
View Patent ↗A transistor epitaxial wafer having: a substrate; an n-type collector layer, a p-type base layer and an n-type emitter layer formed on the substrate in this order; and an n-type InGaAs non-alloy layer having an n-type InGaAs nonuniform composition layer formed on the n-type emitter layer and having an nonuniform indium (In) composition, and an n-type InGaAs uniform composition layer formed on the n-type InGaAs nonuniform composition layer and having a uniform indium (In) composition. The n-type InGaAs nonuniform composition layer has a first layer doped with Si and having a low indium (In) composition, and a second layer formed on the first layer, doped with an n-type dopant except Si, and having an indium (In) composition higher than the first layer.
1. A transistor epitaxial wafer, comprising:
a substrate;
an n-type collector layer, a p-type base layer, and an n-type emitter layer formed on the substrate in this order; and
an n-type InGaAs non-alloy layer comprising an n-type InGaAs nonuniform composition layer formed on the n-type emitter layer and comprising an nonuniform indium (In) composition, and an n-type InGaAs uniform composition layer formed on the n-type InGaAs nonuniform composition layer and comprising a uniform indium (In) composition,
wherein the n-type InGaAs nonuniform composition layer comprises a first layer doped with Si and comprising a low indium (In) composition, and a second layer formed on the first layer, doped with an n-type dopant except Si, and comprising an indium (In) composition higher than the first layer.
2. The transistor epitaxial wafer according to claim 1 , wherein:
the n-type InGaAs nonuniform composition layer comprises a graded layer comprising an In composition gradually increased from 0,
the first layer comprises an In composition of 0 to 0.35,
the second layer comprises an In composition of more than 0.35, and
a final value of the In composition of the second layer near an interface between the second layer and the uniform composition layer is substantially equal to the In composition of the uniform composition layer.
3. The transistor epitaxial wafer according to claim 1 , wherein:
the first layer comprises an In composition of 0 to 0.35, and
the second layer comprises an In composition in the range 0.35 to the In composition of the uniform composition layer.
4. The transistor epitaxial wafer according to claim 1 , wherein:
the first layer comprises a carbon (C) background concentration of not more than 1×10 18 cm −3 at the In composition thereof.
5. The transistor epitaxial wafer according to claim 1 , wherein:
the n-type dopant except Si of the second layer comprises Se or Te.
6. The transistor epitaxial wafer according to claim 1 , wherein:
the second layer comprises a carbon (C) background concentration of not more than 1×10 18 cm −3 at the In composition thereof.
7. The transistor epitaxial wafer according to claim 1 , wherein:
the n-type InGaAs uniform composition layer comprises Se or Te as an n-type dopant thereof.
8. The transistor epitaxial wafer according to claim 1 , wherein:
the substrate comprises GaAs, Si or InP.
9. A transistor epitaxial wafer, comprising:
a substrate;
a buffer layer, an electron donating layer, a channel layer, and a Schottky layer formed on the substrate in this order; and
an n-type InGaAs non-alloy layer comprising an n-type InGaAs nonuniform composition layer formed on the Schottky layer and comprising an nonuniform indium (In) composition, and an n-type InGaAs uniform composition layer formed on the n-type InGaAs nonuniform composition layer and comprising a uniform indium (In) composition,
wherein the n-type InGaAs nonuniform composition layer comprises a first layer doped with Si and comprising a low indium (In) composition, and a second layer formed on the first layer, doped with an n-type dopant except Si, and comprising an indium (In) composition higher than the first layer.
10. The transistor epitaxial wafer according to claim 9 , wherein:
the n-type InGaAs nonuniform composition layer comprises a graded layer comprising an In composition gradually increased from 0,
the first layer comprises an In composition of 0 to 0.35,
the second layer comprises an In composition of more than 0.35, and
a final value of the In composition of the second layer near an interface between the second layer and the uniform composition layer is substantially equal to the In composition of the uniform composition layer.
11. The transistor epitaxial wafer according to claim 9 , wherein:
the first layer comprises an In composition of 0 to 0.35, and
the second layer comprises an In composition in the range 0.35 to the In composition of the uniform composition layer.
12. The transistor epitaxial wafer according to claim 9 , wherein:
the first layer comprises a carbon (C) background concentration of not more than 1×10 18 cm −3 at the In composition thereof.
13. The transistor epitaxial wafer according to claim 9 , wherein:
the n-type dopant except Si of the second layer comprises Se or Te.
14. The transistor epitaxial wafer according to claim 9 , wherein:
the second layer comprises a carbon (C) background concentration of not more than 1×10 18 cm −3 at the In composition thereof.
15. The transistor epitaxial wafer according to claim 9 , wherein:
the n-type InGaAs uniform composition layer comprises Se or Te as an n-type dopant thereof.
16. The transistor epitaxial wafer according to claim 9 , wherein:
the substrate comprises GaAs, Si or InP.
17. A transistor, comprising:
a substrate;
an n-type sub-collector layer, an n-type collector layer, a p-type base layer, and an n-type emitter layer formed on the substrate in this order;
an n-type InGaAs non-alloy layer formed on the emitter layer, comprising an n-type InGaAs nonuniform composition layer and an n-type InGaAs uniform composition layer formed on the n-type InGaAs nonuniform composition layer and comprising a uniform indium (In) composition, the nonuniform composition layer comprising a first layer doped with Si and comprising a low indium (In) composition and a second layer formed on the first layer, doped with an n-type dopant except Si, and comprising an indium (In) composition higher than the first layer;
an emitter electrode formed on the n-type InGaAs uniform composition layer;
a base electrode formed on the p-type base layer; and
a collector electrode formed on the n-type sub-collector layer.