IP Library Granted Patent US 7,427,542
Granted Patent B2
US 7,427,542 · App. 11/639,212 · Granted Sep 23, 2008

Semiconductor device and method of manufacturing the same

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Quick Facts
Patent No.
US 7,427,542
App. No.
11/639,212
Granted
Sep 23, 2008
Kind
B2
Abstract

A method of manufacturing a semiconductor device including a complementary metal oxide semiconductor (CMOS) and a bipolar junction transistor (BJT), the method comprising the steps of: forming a gate oxide layer on a substrate having a p-type and an n-type well; removing the gate oxide layer on the p-type well; forming bases on the p-type well; forming a first photosensitive layer pattern that exposes the bases on the substrate; implanting p-type impurity ions into the bases through the first photosensitive layer pattern; removing the first photosensitive layer pattern; forming a second photosensitive layer pattern that exposes the p-type and the n-type wells; and implanting n-type impurity ions into the p-type and the n-type wells through the second photosensitive layer pattern to form an emitter and a collector, respectively, to form the BJT. Therefore, CMOS manufacturing processes are used to form a high frequency BJT having improved frequency and noise characteristics.

Claims (16)

1. A method of manufacturing a semiconductor device including a complementary metal oxide semiconductor (CMOS) and a bipolar junction transistor (BJT), the method comprising the steps of:

forming a gate oxide layer on a substrate in which a p-type well and an n-type well are formed;

removing the gate oxide layer on the p-type well;

forming bases made of polysilicon on the p-type well;

forming a first photosensitive layer pattern that exposes the bases on the substrate;

implanting p-type impurity ions into the bases through the first photosensitive layer pattern;

removing the first photosensitive layer pattern;

forming a second photosensitive layer pattern that exposes the p-type well and the n-type well on the bases and the substrate; and

implanting n-type impurity ions into the p-type well and the n-type well through the second photosensitive layer pattern to form an emitter and a collector of the BJT.

2. The method of claim 1 , wherein the gate electrode of the CMOS is formed when the bases are formed.

3. The method of claim 1 , wherein p-type impurity ions are implanted into the source and drain regions of a PMOS in the CMOS when the p-type impurity ions are implanted into the bases.

4. The method of claim 1 , wherein n-type impurity ions are implanted into the source and drain regions of the PMOS in the CMOS when the n-type impurity ions are implanted into the p-type well and the n-type well.

5. The method of claim 1 , further comprising the steps of:

forming silicides on the bases, the emitter, and the collector;

forming an insulating layer having contact holes that expose the silicides on the substrate; and

forming base contacts, an emitter contact, and a collector contact for filling the contact holes.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 10, 2019
From: DB HITEK CO., LTD.
To: COLUMBA TECHNOLOGIES INC.
Reel/Frame 049709/0857 →
CHANGE OF NAME Recorded Nov 30, 2017
From: DONGBU HITEK CO., LTD.
To: DB HITEK CO., LTD
Reel/Frame 044555/0913 →
MERGER AND CHANGE OF NAME Recorded Nov 29, 2017
From: DONGBU ELECTRONICS CO., LTD.; DONGBU HITEK CO., LTD.
To: DONGBU HITEK CO., LTD.
Reel/Frame 044533/0523 →