Method for fabricating fully silicided gate
View Patent ↗A method for fabricating a fully silicided gate, including forming a gate dielectric layer on a semiconductor substrate, depositing an amorphous silicon layer on the gate dielectric layer, forming a metallic layer on the amorphous silicon layer, depositing a hard mask on the metallic layer, wherein the amorphous silicon layer and the metal layer are silicided due to a thermal budget applied thereto, thereby forming a metal silicide layer, and patterning the metal silicide layer based on the hard mask to form a gate.
1. A method for fabricating a fully silicided gate, comprising:
forming a gate dielectric layer on a semiconductor substrate;
depositing an amorphous silicon layer on the gate dielectric layer;
forming a metallic layer on the amorphous silicon layer;
depositing a tetraethyl orthosilicate (TEOS) layer on the metallic layer thereby forming a hard mask by patterning the TEOS layer; and
patterning the amorphous silicon layer and the metallic layer based on the hard mask to form a gate,
wherein a thermal budget entailed by said depositing the TEOS layer causes the amorphous silicon layer and the metallic layer to be silicided, thereby forming a metal silicide layer.
2. The method of claim 1 , wherein the metallic layer includes a cobalt (Co) layer.
3. The method of claim 1 , wherein the metallic layer includes a nickel (Ni) layer.
4. A method for fabricating a fully silicided gate, comprising:
forming a gate dielectric layer on a semiconductor substrate;
depositing an amorphous silicon layer on the gate dielectric layer;
forming a metallic layer on the amorphous silicon layer;
depositing a tetraethyl orthosilicate (TEOS) layer on the metallic layer thereby forming a hard mask by patterning the TEOS layer;
patterning the amorphous silicon layer and the metallic layer based on the hard mask to form a gate; and
depositing an ONO (Oxide/Nitride/Oxide) layer on a sidewall of the gate thereby forming a spacer,
wherein a thermal budget entailed by said depositing the TEOS layer causes the amorphous silicon layer and the metallic layer to be silicided, thereby forming a metal silicide layer, and
wherein a thermal budget entailed by said depositing the ONO layer causes the hard mask and the gate to be silicided, thereby forming another metal silicide layer.