Method for manufacturing semiconductor device
View Patent ↗A method for manufacturing a semiconductor device includes forming a plurality of gate lines on a substrate, forming a first cell spacer on the gate lines, forming a second cell spacer on the first cell spacer, forming a buffer layer on the second cell spacer, and exposing the surface of the substrate by etching the buffer layer.
1. A method for manufacturing a semiconductor device comprising:
forming a plurality of gate lines on a substrate;
forming a gate spacer on the gate lines;
forming a first cell spacer on the gate spacer;
forming an insulation layer over the first cell spacer;
etching the insulation layer to form a contact hole opening top portions of the first gate spacer and bottom portions of the first gate spacer between the neighboring gate lines;
forming a second cell spacer on a resultant structure obtained after etching the insulation layer;
forming a buffer layer on the second cell spacer; and
etching the buffer layer, the second cell spacer and the first cell spacer to expose the surface of the substrate between the gate lines,
wherein the first cell spacer is conformally formed on the gate spacer, gate lines and the substrate, and the second cell spacer is formed thinner on the surface of the substrate and sidewalls of the gate spacer than on the top surface of the gate spacer.
2. The method of claim 1 , wherein a thickness ratio between the second cell spacer on the surface of the substrate and the sidewalls of the gate spacer and the second cell spacer on the top surface of the gate spacer is set at approximately 0.8-0.9:0.95-1.
3. The method of claim 1 , wherein the first and second cell spacers include substantially the same material.
4. The method of 3 , wherein the first and second cell spacers include a nitride-based material.
5. The method of claim 4 , wherein the second cell spacer is formed at a low temperature in a range of approximately 200° C. to 400° C.
6. The method of claim 5 , wherein the second cell spacer is formed using N 2 , SiH 4 and NH 3 gases.
7. The method of claim 6 , wherein the N 2 , SiH 4 and NH 3 gases flow at flow rates in a range of approximately 1-2 slm, approximately 0.2-0.6 slm, and approximately 2-5 slm, respectively.
8. The method of claim 1 , wherein the buffer layer is formed thicker on the top surface than on sidewalls of the gate spacer.
9. The method of claim 8 , wherein the buffer layer includes an oxide-based material.
10. The method of claim 9 , wherein the buffer layer includes undoped silicate glass (USG).
11. The method of claim 1 , wherein the etching of the buffer layer, the second cell spacer and the first cell spacer proceeds with employing an etch-back process in a condition that a ratio of an etch selectivity of the buffer layer to the etch selectivity of each of the first and second cell spacers is approximately 1:1.