Semiconductor memory apparatus having noise generating block and method of testing the same

1. A semiconductor memory apparatus comprising:

memory banks, each of which includes a plurality of memory cells;

a peripheral circuit unit that includes a plurality of circuit groups around the memory banks; and

a noise generating block that is disposed in the peripheral circuit unit and selectively applies a noise to the memory banks in a test mode,

wherein the noise generating block includes:

a command decoder that decodes a plurality of commands;

a control unit that generates a noise test control signal corresponding to an output signal of the command decoder; and

a noise generating unit that generates a current according to whether the noise test control signal of the control unit is enabled or not,

wherein the noise test control signal is generated by a signal that sets a noise test mode obtained by decoding the plurality of commands, and a signal that sets an enable interval of the noise test control signal in the noise test mode.

2. The semiconductor memory apparatus of claim 1 ,

wherein the output signal of the command decoder is an enable signal for setting the noise test mode.

3. The semiconductor memory apparatus of claim 1 ,

wherein the output signal of the command decoder is a signal that is generated by decoding a mode register set (mrs) signal.

4. The semiconductor memory apparatus of claim 1 ,

wherein the output signal of the command decoder is a signal that is enabled so as to generate the noise test control signal in the noise test mode.

5. The semiconductor memory apparatus of claim 4 ,

wherein the signal output from the command decoder is a signal that is generated from a CKE (Clock enable) signal or a /CS (chip select) signal.

6. The semiconductor memory apparatus of claim 1 ,

wherein the control unit includes a NAND gate that receives the signal output from the command decoder.

7. The semiconductor memory apparatus of claim 1 ,

wherein the noise generating unit includes:

a delay unit that controls the speed of the noise test control signal which is supplied; and

a current generating unit that generates a current between a first voltage terminal and a second voltage terminal according to the input of the noise test control signal that is supplied from the delay unit.

8. The semiconductor memory apparatus of claim 7 ,

wherein the delay unit is configured in the form of an RC delay unit that includes a resistor and a capacitor.

9. The semiconductor memory apparatus of claim 7 ,

wherein the current generating unit includes a transistor that has a gate terminal which is connected to the delay unit, a drain terminal to which the first voltage is applied, and a source terminal to which the second voltage is applied.

10. The semiconductor memory apparatus of claim 7 ,

wherein the current generating unit includes a plurality of sub current generating units that generate a current between the first voltage terminal and the second voltage terminal.

11. The semiconductor memory apparatus of claim 10 ,

wherein each of the sub current generating units includes:

a first transistor that has a gate to which the output signal of the delay unit is input, and a drain connected to the first voltage terminal; and

a second transistor that has a drain connected to the source of the corresponding first transistor, a gate to which a corresponding current generation signal is input, and a source connected to the second voltage terminal.

12. The semiconductor memory apparatus of claim 7 ,

wherein the first voltage is a voltage supplied from an external power supply VDD, and the second voltage is a ground voltage VSS.

13. A semiconductor memory apparatus comprising:

memory banks, each of which includes a plurality of memory cells;

a peripheral circuit unit that includes a plurality of circuit groups around the memory banks; and

a noise generating block that is disposed in the peripheral circuit unit, which includes a command decoder decoding a plurality of commands, a control unit generating a noise test control signal according to an output signal of the command decoder, and a noise generating unit generating a current according to whether the noise test control signal of the control unit is enabled or not,

wherein the noise generating unit includes a delay unit that controls a supplying speed of the noise test control signal, and at least one transistor that generates a current between a first voltage terminal and a second voltage terminal according to the input of the noise test control signal supplied from the delay unit,

wherein the noise test control signal is generated by a signal that sets a noise test mode obtained by decoding the plurality of commands, and a signal that sets an enable interval of the noise test control signal in the noise test mode.

14. A method of testing a semiconductor memory apparatus, comprising:

generating a noise test control signal by decoding a plurality of commands, when a semiconductor wafer is tested; and

generating a penetrating-current in a transistor that performs a switching operation according to whether the noise test control signal is enabled or not, to create a noise by the penetrating-current,

wherein the noise test control signal is generated by a signal that sets a noise test mode obtained by decoding the plurality of commands, and a signal that sets an enable interval of the noise test control signal in the noise test mode.

15. The method of claim 14 ,

wherein the signal that sets the noise test mode is generated by decoding a mode register set signal.

16. The method of claim 14 ,

wherein the signal that sets the enable interval of the noise test control signal is generated from a CKE (clock enable) signal or a /CS (inverted chip select) signal.

17. The method of claim 14 ,

wherein the through-current is generated by a potential difference between a voltage supplied from an external power supply VDD and a ground voltage VSS.