Row address control circuit in semiconductor integrated circuit and method of controlling row address using the same
View Patent ↗Disclosed are a row addresses control circuit of a semiconductor integrated circuit and method of controlling row addresses using the same. The circuit includes: a pulse generator receiving a bank active signal to generate a bank active pulse signal; a refresh mode input circuit combining the bank active pulse signal with a refresh signal to generate a refresh combination signal; and a plurality of row address control units driving and latching each global row enable signal to convert the global row enable signal to a local row enable signal in response to an input of the refresh combination signal.
1. A row address control circuit for a semiconductor integrated circuit, comprising:
a pulse generator configured to receive a bank active signal and generate a bank active pulse signal;
a refresh mode input circuit configured to combine the bank active pulse signal with a refresh signal and generate a refresh combination signal being sunk to a ground voltage level throughout a refresh mode; and
a plurality of row address control units configured to drive and latch each global row enable signal, receive the refresh combination signal, and convert the global row enable signal into a local row enable signal in response to the refresh combination signal.
2. The row address control circuit for a semiconductor integrated circuit of claim 1 , wherein the bank active pulse signal is enabled to a low level with a shorter enable time than the bank active signal.
3. The row address control circuit for a semiconductor integrated circuit of claim 1 , wherein the refresh combination signal has a same waveform as the bank active pulse signal in a normal mode.
4. The row address control circuit for a semiconductor integrated circuit of claim 1 , wherein the global row enable signal is generated by decoding a row address in an address decoder, and the local row enable signal is a signal for activating a word line of each bank.
5. The row address control circuit for a semiconductor integrated circuit of claim 1 , wherein the refresh mode input circuit comprises:
a first inverter configured to receive the refresh signal and to produce an output signal;
a NAND gate configured to receive the output signal of the first inverter and the bank active pulse signal and to produce an output signal; and
a second inverter configured to receive the output signal of the NAND gate and output the refresh combination signal.
6. The row address control circuit for a semiconductor integrated circuit of claim 1 , wherein the row address control unit comprises:
a first inverter coupled to a first three-stage inverter configured to non-inversely drive a corresponding global row enable signal and output the global row enable signal to a first node when the electric potential of the refresh combination signal is at a low level;
a second inverter coupled to a second three-stage inverter configured to latch the signal applied to the first node when the electric potential of the refresh combination signal is at a high level; and
an inverter chain configured to non-invert the signal applied to the first node and output the signal as the corresponding local row enable signal.
7. A row addresses control circuit for a semiconductor integrated circuit, comprising:
a refresh mode input circuit configured to generate a refresh combination signal having an electric potential of ground level regardless of whether a bank active pulse signal generated from a bank active signal is enabled in a refresh mode decided by a refresh signal; and
a plurality of row address control units configured to drive and latch each global row enable signal and convert the global row enable signal to a local row enable signal in response to an input of the refresh combination signal.
8. The row address control circuit for a semiconductor integrated circuit of claim 7 , wherein the bank active pulse signal is generated from a bank active signal, and enabled to a low level with a shorter enable time than the bank active signal.
9. The row address control circuit for a semiconductor integrated circuit of claim 7 , wherein the refresh combination signal has a same waveform as the bank active pulse signal in a normal mode.
10. The row address control circuit for a semiconductor integrated circuit of claim 7 , wherein the global row enable signal is a signal generated by decoding a row address in an address decoder, and the local row enable signal is a signal for activating a word line of each bank.
11. The row address control circuit for a semiconductor integrated circuit of claim 7 , wherein the refresh mode input circuit comprises:
a first inverter configured to receive the refresh signal and to produce an output signal;
a NAND gate configured to receive an output signal of the first inverter and the bank active pulse signal and to produce an output signal; and
a second inverter configured to receive an output signal of the NAND gate and output the refresh combination signal.
12. The row address control circuit for a semiconductor integrated circuit of claim 7 , wherein the row address control unit comprises:
a first inverter coupled to a first three-stage inverter configured to non-inversely drive a corresponding global row enable signal and output the global row enable signal to a first node when the electric potential of the refresh combination signal is at a low level;
a second inverter coupled to a second three-stage inverter configured to latch the signal applied to the first node when the electric potential of the refresh combination signal is at a high level; and
an inverter chain configured to non-inversely drive the signal applied to the first node and output the signal as the corresponding local row enable signal.
13. A method of controlling row addresses, comprising:
receiving a bank active signal and generating a bank active pulse signal;
combining the bank active pulse signal with a refresh signal and generating a refresh combination signal being sunk to a ground level throughout a refresh mode; and
driving and latching each global row enable signal in response to an input of the refresh combination signal and converting the global row enable signals into respective local row enable signals.
14. The method of controlling row addresses of claim 13 , wherein the bank active pulse signal is enabled to a low level with a shorter enable time than the bank active signal.
15. The method of controlling row addresses of claim 13 , wherein the refresh combination signal has a same waveform as the bank active pulse signal in a normal mode.
16. The method of controlling row addresses of claim 13 , wherein the global row enable signal, is a signal generated by decoding a row address in an address decoder, and the local row enable signal is a signal for activating a word line of each bank.
17. A method of controlling row addresses, comprising:
generating a refresh combination signal having an electric potential of ground level regardless of whether a bank active pulse signal generated from a bank active signal is enabled in a refresh mode decided by a refresh signal; and
driving and latching each global row enable signal in response to an input of the refresh combination signal and converting the global row enable signals into respective local row enable signals.
18. The method of controlling row addresses of claim 17 , wherein the bank active pulse signal is generated from a bank active signal, and enabled to a low level with a shorter enable time than the bank active signal.
19. The method of controlling row addresses of claim 17 , wherein the refresh combination signal has a same waveform as the bank active pulse signal in a normal mode.
20. The method of controlling row addresses of claim 17 , wherein the global row enable signal is a signal generated by decoding a row address in an address decoder, and the local row enable signal is a signal for activating a word line of each bank.