Method for manufacturing semiconductor device

1. A method for forming a semiconductor device, the method comprising:

sequentially depositing a buffer insulation layer and a first insulation layer on a semiconductor substrate having a high voltage device region and a low voltage device region;

removing portions of the buffer insulation layer and the first insulation layer to expose a portion of the high voltage device region;

forming a second insulation layer thicker than the buffer insulation layer in the exposed portion of the high voltage device region;

selectively removing the first insulation layer and the buffer insulation layer from the low voltage device region and the high voltage device region, while masking the second insulation layer and a portion of the buffer insulation layer adjacent to the second insulation layer in the high voltage device region, to expose a portion of the high voltage device region and the entire low voltage device region;

forming a third insulation layer thinner than the buffer insulation layer in the low voltage region and on exposed substrate in the high voltage region; and

forming transistor gates on the second insulation layer in the high voltage device region and on the third insulation layer in the low voltage device region.

2. The method according to claim 1 , wherein removing portions of the buffer insulation layer and the first insulation layer comprises:

coating a first photoresist on the first insulation layer;

patterning the first photoresist such that a portion of the first insulation layer in the high voltage device region is exposed, using exposure and development processes;

etching the exposed portion of the first insulation layer by a predetermined depth using the first photoresist as a mask;

removing the first photoresist and blanket etching the first insulation layer to expose a corresponding portion of the buffer insulation layer; and

removing the exposed portion of the buffer insulation layer using the first insulation layer as a mask.

3. The method according to claim 2 , wherein the buffer insulation layer has a thickness of 100˜200 Å, the first insulation layer has a thickness of 450˜550 Å, and the exposed portion of the first insulation layer is etched to a thickness of 150˜250 Å.

4. The method according to claim 2 , wherein about 150˜250 Å of the first insulation layer is blanket etched by immersing the substrate in a H 3 PO 4 solution.

5. The method according to claim 1 , wherein removing the exposed buffer insulation layer-comprises immersing the substrate in a HF solution.

6. The method according to claim 1 , wherein the second insulation layer has a thickness of 350˜450 Å, and is formed using a thermal oxidation process.

7. The method according to claim 6 , wherein the thermal oxidation process comprises local oxidation of silicon (LOCOS).

8. The method according to claim 1 , wherein selectively removing the first insulation layer and the buffer insulation layer comprises:

removing the first insulation layer to expose the buffer insulation layer;

coating a second photoresist on the buffer insulation layer;

patterning the second photoresist using exposure and development processes such that the patterned second photoresist covers the second insulation layer and has a greater width than that of the second insulation layer; and

removing an exposed portion of the buffer insulation layer using the patterned second photoresist as a mask.

9. The method according to claim 8 , wherein the first insulation layer is removed to a target thickness of 150˜250 Å by immersion in a H 3 PO 4 solution.

10. The method according to claim 8 , wherein the buffer insulation layer is removed by 100˜200 Å or more by immersion in a HF solution.

11. The method according to claim 1 , wherein forming the transistor gates comprises:

depositing a polysilicon layer on the second and third insulating layers; and

forming gate electrodes using a gate electrode forming mask in the high and low voltage device regions.

12. The method according to claim 11 , further comprising forming source and drain regions at lateral sides of the gate electrodes.

13. The method according to claim 12 , further comprising forming a salicide layer in the source and drain regions.

14. The method according to claim 13 , further comprising forming source and drain electrodes to contact the salicide layer in the respective source and drain regions.

15. The method according to claim 1 , wherein masking the second insulation layer and the portion of the buffer insulation layer comprises forming a patterned photoresist on the second insulation layer and the buffer insulation layer.

16. The method according to claim 15 , wherein the patterned photoresist on the second insulation layer has a width greater than that of the second insulation layer.