Method for on chip sensing of SONOS V
View Patent ↗A system and method for determining a SONOS V T window using a current sensing scheme is disclosed. The present invention creates a first current path and a second current path through the volatile and non-volatile sections of an nvSRAM memory cell. The erase threshold voltage of the first edge of the window is determined when current is detected in the first path. The program voltage of the second edge of the window is determined when current is detected in the second path. Accordingly, the voltage used to power a plurality of SONOS transistors may be set using the values of the first and second threshold edges to determine the V T window.
1. A method for determining a SONOS V T window in a non-volatile SRAM having a volatile portion and a non-volatile portion, said method comprising:
creating a first current path from a first tri-gate structure to a first location, said first tri-gate structure having a first recall transistor, a first store transistor and a first SONOS transistor, each transistor having a gate node, a source node and a drain node, said first current path including a first data node within said volatile portion, said first location having a current monitoring means for detecting current on said first current path;
creating a second current path from a second tri-gate structure to a second location, said second tri-gate structure having a second recall transistor, a second store transistor and second SONOS transistor, each transistor having a gate node, a source node and a drain node, said second current path including a second data node within said volatile portion, said second location having a current monitoring means for detecting current on said second current path;
ramping a voltage applied to said gate nodes of said first and second SONOS transistors;
detecting current on said first current path to determine an erase threshold voltage;
detecting the presence of current on said second current path to determine the program threshold voltage; and
determining the V T window of said first and second SONOS transistors based upon said erase threshold voltage and said program threshold voltage.
2. The method of claim 1 further comprising:
setting a first voltage to an on state that is applied to said gate nodes of said first recall transistor and said second recall transistor; and
setting a second voltage to an on state that is applied to said gate nodes of said first store transistor and said second store transistor.
3. The method of claim 1 further comprising:
setting a word line to ground that is coupled to said volatile portion of said non-volatile SRAM.
4. The method of claim 1 wherein said current monitoring means for detecting current on said first current path includes a current monitoring device, and
wherein said current monitoring means for detecting current on said second current path includes a current monitoring device.
5. A method for determining a voltage to apply to the gate nodes of a plurality of SONOS transistors for a RECALL operation within a non-volatile SRAM having a volatile portion and a non-volatile portion, said method comprising:
creating a first current path from each erase tri-gate structure in said non-volatile portion to a first location, said erase tri-gate structure having a recall transistor, a store transistor and a SONOS transistor, said first current path including a data node within said volatile portion, said first location having a current monitoring device for detecting current on said first current path;
creating a second current path from each program tri-gate structure in said non-volatile portion to a second location, said program tri-gate structure having a recall transistor, a store transistor and a SONOS transistor, said second current path including a second data node within said volatile portion, said second location having a current monitoring device for detecting current on said second current path;
ramping a voltage applied to said gate nodes of each SONOS transistors from an initial voltage to a terminating voltage;
detecting current on said first current path to determine an erase threshold voltage;
detecting a range of voltages where current in said first current path does not increase when said voltage applied to said SONOS transistor is ramped;
detecting current within said second current path to determine a program threshold voltage; and
setting said voltage to apply to said gate nodes of said plurality of SONOS transistors between said erase threshold voltage and said program threshold voltage.
6. The method of claim 5 further comprising:
setting a first voltage to an on state that is applied to said recall transistor of said erase tri-gate structure and to said recall transistor of said program tri-gate structure; and
setting a second voltage to an on state that is applied to said store transistor of said erase tri-gate structure and to said store transistor of said program tri-gate structure.
7. The method of claim 5 further comprising:
setting a word line to ground that is coupled to said volatile portion of said non-volatile SRAM.