Multi-port memory device
View Patent ↗A multi-port memory device includes: a bank having a plurality of matrices; a plurality of test data input/output units where data is input/output using a test mode for detecting a defective memory cell; a plurality of ports converted into a decoding device for decoding a command/address at the test mode; a plurality of data transfer lines for transferring data between the matrices and the test data I/O units, wherein the data transfer lines is grouped into the number of matrices; and a plurality of temporary storing units included between the data transfer lines and the matrices for temporarily storing data.
1. A multi-port memory device, comprising:
a bank having a plurality of matrices;
a plurality of test data input/output (I/O) units which input/output data in a test mode, and not in a normal mode, for detecting a defective memory cell;
a plurality of ports converted into a decoding device for decoding a command/address at the test mode, and to input/output commands, addresses and data at a normal mode;
a plurality of data transfer lines for transferring data between the matrix and the test data I/O units, wherein the data transfer lines are grouped into the number of matrices; and
a plurality of temporary storing units included between the data transfer lines and the matrices for temporarily storing data.
2. The multi-port memory device as recited in claim 1 , further comprising a bank control unit for controlling the bank.
3. The multi-port memory device as recited in claim 2 , wherein the data transfer lines include:
global input/output lines included between the test data I/O units and the bank control unit for transferring data; and
global/bank connection lines included between the global input/output lines and the matrices for transferring the data.
4. The multi-port memory device as recited in claim 3 , wherein each of the global input lines and the global output lines includes 16 lines.
5. The multi-port memory device as recited in claim 4 , wherein the global/bank connection lines include:
first global/bank connection lines respectively connected to the global input lines; and
second global/bank connection lines respectively connected to the global output lines.
6. The multi-port memory device as recited in claim 5 , wherein the number of the temporary storing units corresponds to the number of matrices.
7. The multi-port memory device as recited in claim 6 , wherein the global/bank connection lines are in groups of 4 lines, each group connected to a respective temporary storing unit.
8. The multi-port memory device as recited in claim 5 , wherein the temporary storing unit includes:
a write data temporary storing unit for temporarily storing write data for a write operation of the test mode; and
a read data temporary storing unit for temporarily storing read data for a read operation of the test mode.