Electrostatic discharge protection circuit protecting thin gate insulation layers in a semiconductor device

1. An electrostatic discharge (ESD) protection circuit for protecting an internal circuit of a semiconductor, the ESD protection circuit being installed between an input/output pad and an input buffer including a first NMOS transistor, the ESD protection circuit comprising:

a first electrostatic protection unit connected to a power source supply pad, wherein the first electrostatic protection unit discharges an ESD current into the power source supply pad when an ESD is introduced into the input/output pad, and generates a first driving voltage by utilizing the ESD current flow through a voltage-drop unit;

a driver driven by the first driving voltage, wherein the driver generates a second driving voltage by an ESD current; and

a second electrostatic protection unit driven by the second driving voltage for discharging the introduced ESD current into the power source supply such that a voltage applied to a gate of the first NMOS transistor is reduced;

wherein the power source supply pad includes a power source voltage supply pad and a ground voltage supply pad,

wherein the second electrostatic protection unit includes a second NMOS transistor having a drain connected to the gate of the first NMOS transistor and the input/output pad, a source connected to the ground voltage supply pad, a substrate connected to the source, and a gate connected to the driver, and

wherein the driver comprises:

a PMOS transistor having a source and a substrate connected to the input/output pad, a gate connected to the power source voltage supply pad, and a drain connected to the gate of the second NMOS transistor; and

a resistor having a first end connected to the drain of the PMOS transistor and a second end connected to the ground voltage supply pad.

2. The ESD protection circuit as claimed in claim 1 , wherein the first electrostatic protection unit includes the voltage-drop unit between the input/output pad and the source of the PMOS transistor.

3. The ESD protection circuit as claimed in claim 2 , wherein the voltage-drop unit includes at least one diode.

4. The ESD protection circuit as claimed in claim 2 , wherein the voltage-drop unit includes a diode and at least one resistor.

5. The ESD protection circuit as claimed in claim 2 , wherein the voltage-drop drop unit comprises:

a first diode installed between the input/output pad and the source of the PMOS transistor;

a second diode connected in parallel to the first diode; and

at least one resistor connected in series to the second diode.

6. The ESD protection circuit as claimed in one of claims 1 to 5 , wherein the first electrostatic protection unit comprises:

a capacitor having a first end of the capacitor connected to the power source voltage supply pad;

a resistor having a first end connected to a second end of the capacitor, and a second end connected to the ground voltage supply pad; and

a third NMOS transistor having a drain connected to the power source voltage supply pad, a gate connected to the first end of the resistor, a source connected to the ground voltage supply pad, and a substrate connected to the source.

7. An electrostatic discharge (ESD) protection circuit for protecting an internal circuit of a semiconductor, the ESD protection circuit being installed between an input/output pad and an input buffer including a first NMOS transistor, the ESD protection circuit comprising:

a first electrostatic protection unit connected to a power source supply pad, wherein the first electrostatic protection unit discharges an ESD current into the power source supply pad when an ESD is introduced into the input/output pad, and generates a first driving voltage, and generates a second driving voltage by utilizing the ESD current flow through a voltage-drop unit;

a driver driven by the second driving voltage, wherein the driver generates a third driving voltage by using an ESD current; and

a second electrostatic protection unit driven by the first driving voltage and the third driving voltage for discharging the introduced ESD current into the power source supply pad such that a voltage applied to a gate of the first NMOS transistor is reduced;

wherein the power source supply pad includes a power source voltage supply pad and a around voltage supply pad,

wherein the second electrostatic protection unit includes a second NMOS transistor having a drain connected to the gate of the first NMOS transistor and the input/output pad, a source connected to the ground voltage supply pad, a substrate connected to the source, and a gate connected to the driver, and

wherein the driver includes a PMOS transistor having a source and a substrate connected to the input/output pad, a gate connected to the power source voltage supply pad, and a drain connected to the gate of the second NMOS transistor.

8. The ESD protection circuit as claimed in claim 7 , wherein the first electrostatic protection unit comprises:

a third NMOS transistor having a drain connected to the power source supply pad, a gate connected to both the drain of the PMOS transistor and the gate of the second NMOS transistor, a source connected to the ground supply pad, and a substrate of connected to the source;

a capacitor having a first end connected to the power source voltage supply pad, and a second end connected to the gate of the third NMOS transistor; and

a resistor having a first end connected to the second end of the capacitor, a second end connected the ground voltage supply pad, wherein the first electrostatic protection unit applies the first driving voltage applied to both ends of the resistor to the gate of the second NMOS transistor when an ESD current is discharged into the ground voltage supply pad.

9. The ESD protection circuit as claimed in claim 8 , wherein the first electrostatic protection unit includes the voltage-drop unit between the input/output pad and the source of the PMOS transistor.

10. The ESD protection circuit as claimed in claim 9 , wherein the voltage-drop unit includes at least one diode.

11. The ESD protection circuit as claimed in claim 10 , wherein the voltage-drop unit includes a diode and at least one resistor.

12. The ESD protection circuit as claimed in claim 10 , wherein the voltage-drop unit comprises:

a first diode installed between the input/output pad and the source of the PMOS transistor;

a second diode connected in parallel to the first diode; and at least one resistor connected in series to the second diode.