Circuit pattern exposure method and mask
View Patent ↗A circuit pattern exposure method for irradiating illumination light onto a mask to transfer (offset) mask patterns that are formed in the mask to a semiconductor substrate, wherein the mask includes a plurality of main mask patterns that are arranged at a prescribed pitch and auxiliary mask patterns that are arranged outside the outermost main mask pattern and that are not to be transferred (offset) to the semiconductor substrate; the auxiliary mask patterns are provided with a first auxiliary mask row that is arranged adjacent to the outermost main mask pattern and a second auxiliary mask row that is arranged adjacent to the first auxiliary mask row; and the first auxiliary mask row and the second auxiliary mask row are arranged at a pitch that is narrower than the pitch of arrangement of the main mask patterns.
1. A circuit pattern exposure method for irradiating illumination light onto a mask to transfer (offset) mask patterns that are formed on the mask onto a semiconductor substrate, wherein:
said mask comprises a main mask pattern that is transferred onto said semiconductor substrate and an auxiliary mask pattern that is arranged adjacently to the main mask pattern and that is not transferred onto said semiconductor substrate;
said main mask pattern has a first pitch defined by a line and a space; and
said auxiliary mask pattern includes a first auxiliary mask pattern and a second auxiliary mask pattern between the main mask pattern and the first auxiliary mask pattern, the first auxiliary mask pattern having a second pitch defined by a line and a space, the second auxiliary mask pattern having a third pitch defined by a line and space, each of the second and third pitches being smaller than the first pitch.
2. A circuit pattern exposure method for irradiating illumination light onto a mask to transfer (offset) mask patterns that are formed on the mask onto a semiconductor substrate, wherein:
said mask comprises a plurality of main mask patterns that are arranged at a prescribed first pitch and an auxiliary mask pattern that is arranged outside an outermost main mask pattern and that is not transferred onto said semiconductor substrate;
said auxiliary mask pattern is composed of a first auxiliary mask row that is arranged adjacent to the outermost main mask pattern and a second auxiliary mask row that is arranged adjacent to the first auxiliary mask row; and
said first auxiliary mask row and said second auxiliary mask row are formed by a plurality of micro-masks arranged along said main mask patterns, and are arranged at a first pitch and a second pitch, respectively, said first pitch and second pitch each being narrower pitch than the first pitch of the arrangement of said main mask patterns.
3. The circuit pattern exposure method according to claim 2 , wherein the micro-masks that form said second auxiliary mask row are larger than the micro-masks that form said first auxiliary mask row.
4. The circuit pattern exposure method according to claim 2 , wherein the spacing of the arrangement of the plurality of micro-masks that form said second auxiliary mask row is narrower than the spacing of the arrangement of the plurality of micro-masks that form said first auxiliary mask row.
5. The circuit pattern exposure method according to claim 1 , wherein the width of an outermost main mask pattern is greater than the width of other main mask patterns.
6. A mask in which mask patterns are formed that are to be transferred (offset) onto a semiconductor substrate; said mask comprising:
a plurality of main mask patterns that are arranged at a first prescribed pitch and an auxiliary mask pattern that is arranged outside an outermost main mask pattern and that is not transferred (offset) to said semiconductor substrate;
wherein said auxiliary mask pattern is composed from a first auxiliary mask row that is arranged adjacent to said outermost main mask pattern at a second pitch and a second auxiliary mask row that is arranged adjacent to said first auxiliary mask row at a third pitch, and said second pitch and said third pitch are each narrower than said first pitch.
7. The mask according to claim 6 , wherein the width of an outermost main mask pattern is greater than the width of the other main mask patterns.
8. A mask in which mask patterns are formed that are to be transferred (offset) to a semiconductor substrate; said mask comprising:
a plurality of main mask patterns arranged at a prescribed first pitch, and an auxiliary mask pattern that is arranged outside the outermost main mask pattern and that is not to be transferred (offset) to said semiconductor substrate;
wherein said auxiliary mask pattern is composed of a first auxiliary mask row that is arranged adjacent to said outermost main mask pattern and a second auxiliary mask row arranged adjacent to said first auxiliary mask row; and
said first auxiliary mask row and said second auxiliary mask row are formed by a plurality of micro-masks arranged along said main mask patterns, and are arranged at a first pitch and a second pitch, respectively, said first pitch and second pitch each being narrower pitch than the first pitch of the arrangement of said main mask patterns.
9. The mask according to claim 8 , wherein micro-masks that form said second auxiliary mask row are larger than micro-masks that form said first auxiliary mask row.
10. The mask according to claim 8 , wherein the spacing of the arrangement of the plurality of micro-masks that form said second auxiliary mask row is narrower than the spacing of the arrangement of the plurality of micro-masks that form said first auxiliary mask row.