Formation of an integrated circuit structure with reduced dishing in metallization levels
View Patent ↗An integrated circuit structure includes a metallization level having a dual damascene trench structure formed in a layer of dielectric material. The dielectric material has an upper surface with a first degree of planarity. The metallization level includes a conductive layer formed in the trench structure with an upper surface characterized by the same level of planarity as the dielectric material upper surface. In certain embodiments, the upper surface of the conductive layer is substantially coplanar with the dielectric material upper surface.
1. A method of fabricating an integrated circuit structure, comprising:
defining a damascene structure in dielectric material;
forming a layer of etch stop material on an upper surface of the dielectric material;
forming a layer of conductive material in the damascene structure and over a least a portion of an upper surface of the layer of etch stop material;
removing at least a portion of the layer of conductive material until an upper surface of the layer of conductive material is substantially coplanar with the upper surface of the layer of etch stop material, wherein one or more dished regions are formed in the upper surface of the layer of conductive material, a lowest portion of the one or more dished regions being spaced above the upper surface of the layer of etch stop material;
forming a layer of planarizing material in at least a portion of the one or more dished regions such that an upper surface of the layer of planarizing material is substantially coplanar with the upper surface of the layer etch stop material;
removing at least a portion of the layer of etch stop material until at least a portion of sidewalls of the one or more dished regions are expose above a newly exposed upper surface of the layer of etch stop material;
removing at least a portion of the upper surface of the layer of conductive material until the upper surface of the layer of conductive material is substantially coplanar with the newly exposed upper surface of the layer of etch stop material.
2. The method according to claim 1 , wherein the step of forming the layer of planarizing material in at least a portion of one or more dished regions in the conductive material comprises forming the layer of planarizing material such that a cross-sectional thickness of the layer of planarizing material is greater at a lowest portion of the one or more dished regions compared to a cross- sectional thickness of the layer of the planarizing material at an edge of the one or more dished region.
3. The method according to claim 1 , wherein the removal of the portion of the upper surface of the layer of conductive material is accomplished by chemical mechanical polishing.
4. The method according to claim 1 , wherein the fabrication occurs over a semiconductor wafer having transistor devices formed thereon.
5. The method according to claim 1 , wherein the fabrication occurs for multiple metallization levels.
6. The method according to claim 1 , wherein the removal of the portion of the upper surface of conductive material comprises removing the layer of the planarizing material in the one or more dished regions in the conductive material.
7. The method according to claim 1 , wherein the dielectric material comprises a capping layer.
8. An integrated circuit structure comprising:
a damascene structure defined in dielectric material;
a layer of etch stop material formed on an upper surface of the dielectric material;
a layer of conductive material formed by the steps of:
forming the layer of conductive material in the damascene structure and over at least a portion of an upper surface of the layer of etch stop material;
removing at least a portion of the layer of conductive material until an upper surface of the layer of conductive material is substantially coplanar with the upper surface of the layer of etch stop material, wherein one or more dished regions are formed in the upper surface of the layer of conductive material, a lowest portion of the one or more dished regions being spaced above the upper surface of the layer of etch stop material;
forming a layer of planarizing material in at least of the one or more dished regions such that an upper surface of the layer of planarizing material is substantially coplanar with the upper surface of the layer of etch stop material;
removing at least a portion of the layer of etch stop material until at least a portion of sidewalls of the one or more dished regions are exposed above a newly exposed upper surface of the layer of etch stop material;
removing at least a portion of the upper surface of the layer of conductive material until the upper surface of the layer of conductive material is substantially coplanar with the newly exposed upper surface of the layer of etch stop material.
9. The structure according to claim 8 , wherein the step of forming the layer of planarizing material in at least a portion of one or more dished regions in the conductive material comprises forming the layer of planarizing material such that a cross-sectional thickness of the layer of planarizing is greater at a lowest portion of the one or more dished regions compared to a cross-sectional thickness of the layer of planarizing material at an edge of the one or more dished regions.
10. The structure according to claim 8 , wherein the removal of the portion of the upper surface of the layer of conductive material is accomplished by chemical mechanical polishing.
11. The structure according to claim 8 , wherein the structure further comprises:
a layer of semiconductive material having transistors devices formed therein.
12. The structure according to claim 8 , wherein the structure has multiple metallization levels.
13. The structure according to claim 8 , wherein the removal of the portion of the upper surface of the layer of conductive material comprises removing the layer of the planarizing material in the one or more dished regions in the conductive material.
14. The structure according to claim 8 , wherein the dielectric material comprises a capping layer.