Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductor applications
A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal oxide is deposited over the charge trapping layer to form a thick oxide on top of the core source/drain region and a pinch off and a void at the top of the STI trench. An etch is performed on the pinch-off oxide and the thin oxide on the trapping layer on the STI oxide. The trapping layer is then partially etched between the core cells. A dip-off of the oxide on the trapping layer is performed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide and thus isolate the trap layer.
1. A method for manufacturing a memory device, comprising:
performing a shallow trench isolation (STI) process on a semiconductor material to form a plurality of active regions and a plurality of isolation regions, the plurality of active regions being formed to comprise a plurality of exposed corners;
forming a plurality of charge trapping structures over the plurality of active, regions, wherein the plurality of charge trapping structures are self-aligned;
separating the plurality of charge trapping structures at their respective bottom portions such that the respective bottom portions of the plurality of charge trapping structures are separated by a distance that is greater than the distance separating respective top portions of the plurality of charge trapping structures;
forming a first layer of semiconductor or conductive material over the plurality of charge trapping structures,
wherein the shallow trench isolation process is performed before the plurality of charge trapping structures is formed; and
further wherein, a rounding process is performed on the plurality of exposed corners of the active region after the shallow trench isolation process is performed.
2. The method of claim 1 , wherein the plurality of charge trapping structures is self-aligned by:
depositing a non-conformal oxide layer over a charge trapping layer, wherein the non-conformal oxide layer forms a pinch-off and void region over an STI trench;
opening up the pinch-off region by etch; and
partially etching to separate the trapping structure layer between a plurality of cells for isolation in subsequent top oxide step.
3. The method of claim 2 further comprising:
forming a thin conformal sacrificial top oxide over the charge trapping layer before depositing the non-conformal oxide layer; and
etching the thin sacrificial top oxide over the STI trench but leaving a thick residual oxide over the active region.
4. The method of claim 2 further comprising:
forming a top oxide on a portion of the charge trapping layer and converting the remaining portion of the trap layer to oxide to completely separate the trapping layer for each cell.
5. The method of claim 1 , wherein forming a charge trapping structure comprises:
forming a bottom oxide layer over the active region;
forming a nitride layer over the first oxide layer; and
forming a top block oxide layer over the nitride layer.
6. The method of claim 5 , wherein the nitride layer is comprised of silicon rich nitride.
7. The method of claim 5 , wherein the nitride layer is comprised of nitride on top of silicon rich nitride.
8. The method of claim 5 , wherein the nitride layer is comprised of a plurality of layers of nitride, the plurality of layers comprising different percentages of silicon content.
9. The method of claim 1 further comprising:
fabricating a top oxide layer;
masking an ONO structure;
etching the ONO structure;
fabricating a first periphery gate oxide layer;
etching the periphery gate oxide layer; and
fabricating a second periphery gate oxide layer, wherein the second periphery gate oxide layer is thinner than the first periphery gate oxide layer.
10. The method of claim 9 further comprising:
depositing polysilicon after the second periphery gate oxide layer;
defining word lines; and
etching the top oxide layer and trapping layer between word lines.
11. A memory device, comprising:
a semiconductor substrate;
a plurality of active regions;
a plurality of corners comprised on the plurality of active regions;
a plurality of trenches separating the active regions; and
a plurality of self-aligned charge trapping structures disposed over the plurality of active regions, wherein the charge trapping structures are separated at their respective bottom areas such that the respective bottom portions of the plurality of charge trapping structures are separated by a distance that is greater than the distance separating respective top portions of the plurality of charge trapping structures;
further wherein, a rounding process is performed on the plurality of corners comprised on the plurality of active regions before the plurality of self-aligned charge trapping structures are disposed over the plurality of active regions.
12. The memory device of claim 11 , wherein the plurality of self-aligned charge trapping structures is formed through a process of depositing a non-conformal oxide layer over a charge trapping layer, wherein the non-conformal oxide layer forms a pinch-off region and a void over an STI trench, etching the pinch-off region, and etching to separate the trapping structure layer between a plurality of cells.
13. The memory device of claim 12 , wherein a thin conformal sacrificial top oxide is formed over the charge trapping layer before depositing the non-conformal oxide layer.
14. The memory device of claim 11 , wherein the charge trapping structures comprise an oxide-nitride-oxide structure.
15. The memory device of claim 14 , wherein the nitride of the oxide-nitride-oxide structure is comprised of silicon rich nitride.