Rotational positioner and methods for semiconductor wafer test systems
View Patent ↗A semiconductor wafer prober is configured to rotate a semiconductor wafer into relative alignment with a wafer-interface probe adapted to simultaneously probe a number of integrated circuits within a sector of the semiconductor wafer. The wafer can include integrated circuits having different orientations, such that all of the integrated circuits within a given sector being tested have the same orientation. For example, a semiconductor wafer can include two semicircular sectors, with the integrated circuits on either sector having a common orientation rotated 180 degrees from a common orientation of the integrated circuits of the other sector. A wafer-interface probe, or probe card, adapted to test the entire semicircular sector during a single touch down is able to test the entire wafer with one rotational translation between testing.
1. A semiconductor tester adapted for testing a semiconductor wafer including a plurality of integrated circuits arranged in a lattice, the semiconductor tester comprising:
a wafer-interface probe having at least three contact patterns arranged in a non-rectangular, two-dimensional array, each contact pattern adapted to interface with a corresponding bonding pad pattern of a respective one of a plurality of integrated circuits disposed in a lattice on the semiconductor wafer, the two-dimensional array of contact patterns covering at least a 90 degree sector and no more than a 180 degree sector of the semiconductor wafer; and
a rotary wafer handler rotating the semiconductor wafer relative to the wafer-interface probe between tests, bringing each of the at least three contact patterns into simultaneous alignment with a bonding pad pattern of a respective one of a plurality of integrated circuits, each of the at least three contact patterns providing electrical interconnection with a respective one of the aligned bonding pad patterns.
2. The tester of claim 1 , wherein the rotary wafer handler rotates the semiconductor wafer about 90 degrees between tests, the plurality of integrated circuits aligned with the at least three respective contact patterns of the wafer-interface probe approximating one quadrant of the semiconductor wafer.
3. The tester of claim 1 , wherein the rotary wafer handler rotates the semiconductor wafer about 180 degrees between tests, the plurality of integrated circuits aligned with the at least three respective contact patterns of the wafer-interface probe approximating one half of the semiconductor wafer.
4. The tester of claim 1 , wherein the rotary wafer handler rotates the semiconductor wafer by a predetermined angle between tests, the plurality of integrated circuits aligned with the at least three respective contact patterns of the wafer-interface probe approximating a contiguous sector of the semiconductor wafer.
5. The tester of claim 4 , wherein the lattice of integrated circuits disposed on the semiconductor wafer is non-rectangular.
6. The tester of claim 5 , wherein the at least three contact patterns of the wafer-interface probe are arranged in a wedge-shaped configuration.
7. The tester of claim 1 , wherein the at least three contact patterns of the wafer-interface probe are arranged in a non-rectangular configuration.
8. The tester of claim 1 , wherein the rotary wafer handler comprises a vertical displacement stage urging the semiconductor wafer toward the wafer-interface probe ensuring that each of the at least three contact patterns touches an aligned bonding pad pattern of a respective one of a plurality of integrated circuits prior to test.
9. A wafer-interface probe comprising a plurality of contact patterns arranged in a non-rectangular, two-dimensional array, each contact pattern adapted to interface with a corresponding bonding pad pattern of a respective one of a plurality of integrated circuits of a semiconductor wafer, wherein the non-rectangular, two-dimensional array comprises a wedge shape, the two-dimensional array of contact patterns covering at least a 90 degree sector and no more than a 180 degree sector of the semiconductor wafer.