Semiconductor device and method of manufacturing the same
View Patent ↗Example embodiments are directed to a method of manufacturing a semiconductor device and a semiconductor device including a substrate including a plurality of active regions and a plurality of isolation regions between adjacent active regions, each active region including a groove, a bottom surface of the groove being below an upper surface of the active region.
1. A semiconductor device, comprising:
a substrate including a plurality of active regions and a plurality of isolation regions between adjacent active regions, each active region including a groove, a bottom surface of the groove being below an upper surface of the active region and a sidewall of the groove being apart from the isolation regions; and
a gate structure having a floating gate and a control gate, the floating gate in the groove and protruding from a top surface of the active region while being spaced apart from adjacent isolation regions and the control gate facing sidewalls of the floating gate, wherein sidewalls and a bottom surface of the groove facing the floating gate act as a channel region of a transistor, and the groove extends along a direction perpendicular to a longitudinal direction of the gate structure, and each of a source region and a drain region adjacent to the gate structure has a “U”-shape.
2. The semiconductor device of claim 1 , wherein the gate structure is a floating gate structure including a tunneling insulation layer in the groove, the floating gate on the tunneling insulation layer, a blocking insulation layer on the floating gate, and the control gate on the blocking insulation layer.
3. The semiconductor device of claim 2 , wherein the tunneling insulation layer is made of a material selected from the group consisting of silicon oxide, silicon nitride, aluminum oxide, and hafnium oxide.
4. The semiconductor device of claim 1 , further comprising a spacer and a pad oxide between the floating gate and the isolation regions.
5. The semiconductor device of claim 4 , wherein the spacer and the pad oxide are made of silicon oxide.
6. The semiconductor device of claim 1 , wherein a shape of a bottom portion of the groove has an obtuse or rounded profile.
7. The semiconductor device of claim 1 , wherein the groove is in a center portion of the active region.
8. The semiconductor device of claim 1 , wherein a width of the floating gate is substantially equal to that of the groove.
9. The semiconductor device of claim 1 , wherein the floating gate is insulated from the plurality of isolation regions.
10. The semiconductor device of claim 1 , wherein the control gate crosses over the plurality of isolation regions, and a distance between adjacent floating gates under the control gate being larger than a width of an isolation region therebetween.
11. The semiconductor device of claim 1 , wherein the floating gate has a height that is greater than a depth of the groove.
12. A semiconductor device, comprising:
a substrate including a plurality of active regions and a plurality of isolation regions between adjacent active regions, each active region including a groove, a bottom surface of the groove being below an upper surface of the active region and a sidewall of the groove being apart from the isolation regions; and
a gate structure having a conductive pattern and a control gate, the conductive pattern in the groove and protruding from a top surface of the active region while being spaced apart from adjacent isolation regions and the control gate facing sidewalls of the conductive pattern, wherein sidewalls and a bottom surface of the groove facing the conductive pattern act as a channel region of a transistor, and the groove extends along a direction perpendicular to a longitudinal direction of the gate structure, and each of a source region and a drain region adjacent to the gate structure has a “U”-shape.
13. The semiconductor device of claim 12 , wherein major axes of the plurality of active regions and a major axis of the groove are in the same direction.
14. The semiconductor device of claim 12 , wherein a width of the conductive pattern is substantially equal to that of the groove.
15. The semiconductor device of claim 12 , wherein the conductive pattern is insulated from the plurality of isolation regions.
16. The semiconductor device of claim 12 , wherein the control gate crosses over the plurality of isolation regions, and a distance between adjacent conductive patterns under the control gate being larger than a width of an isolation region therebetween.
17. The semiconductor device of claim 12 , wherein a shape of a bottom portion of the groove has an obtuse or rounded profile.
18. The semiconductor device of claim 12 , wherein the conductive pattern has a height that is greater than a depth of the groove.