IP Library Granted Patent US 7,673,387
Granted Patent B2
US 7,673,387 · App. 11/659,190 · Granted Mar 9, 2010

Manufacture of a layer including a component

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Quick Facts
Patent No.
US 7,673,387
App. No.
11/659,190
Granted
Mar 9, 2010
Kind
B2
Abstract

A method for manufacturing a circuit-board layer on a base surface ( 2 ), which base surface ( 2 ) includes conductor patterns ( 19 ). The circuit-board layer being manufactured comprises a conductor-pattern layer ( 14 ), an insulating layer ( 1 ), and at least one component ( 6 ) inside the insulating-material layer ( 1 ). According to the invention, the component ( 6 ) is attached to the conductor layer ( 4 ), the conductor layer ( 4 ) is aligned relative to the base surface ( 2 ) attached with the aid of an insulating material ( 1 ) to the base surface ( 2 ). An insulating-material layer ( 1 ) is thus formed between the conductor layer ( 4 ) and the base surface ( 2 ), on which the said at least one component ( 6 ) is located. Electrical contacts are formed between the contact areas ( 7 ) of the component ( 6 ) and the conductor layer ( 4 ), in such a way that contact openings ( 17 ) are opened at the positions of the contact areas ( 7 ) of the component ( 6 ) and conductive material is made in the contact openings ( 17 ). The conductor layer ( 4 ) is patterned to form a conductor-pattern layer ( 14 ), and at least one via ( 20 ) is made between the conductor-pattern layer ( 14 ) and the conductor patterns ( 19 ) of the base surface ( 2 ).

Claims (33)

1. A method for manufacturing a circuit-board layer on a base surface the base surface including conductor patterns, and the circuit-board layer including a conductor pattern layer, an insulating-material layer, and inside the insulating-material layer at least one component, the method comprising:

providing a conductor layer with contact openings positioned according to the contact areas of the at least one component;

after providing the contact openings, attaching said at least one component to the conductor layer, on the side of a first surface of the conductor layer with the contact areas facing the contact openings in the conductor layer;

aligning the conductor layer relative to the base surface and attaching the conductor layer with the aid of an insulating material to the base surface, the first surface of the conductor layer facing towards the base surface, thereby forming the insulating-material layer between the conductor layer and the base surface, said at least one component being located in said insulating-material layer;

forming electrical contacts between the contact areas of the component and the conductor layer through the contact openings in the conductor layer, wherein the forming includes making conductive material in the contact openings;

patterning the conductor layer to form a conductor-pattern layer; and

making at least one via between the conductor-pattern layer and the conductor patterns of the base surface.

2. The method according to claim 1 , wherein the base surface is the surface of a circuit board.

3. The method according to claim 1 , further comprising:

attaching the component, to the conductor layer with the aid of an insulating adhesive; and

after the attachment forming the electrical contact between the conductor layer and the contact areas, by making vias through the insulating adhesive.

4. The method according to claim 3 , wherein the step of forming the electrical contacts between the contact areas of the component and the conductor layer is performed after said step of attaching the conductor layer to the base surface with the aid of insulating material.

5. The method according to claim 1 , wherein the step of making the conductive material in the contact openings comprises using a chemical metallization method and/an electrochemical metallization method.

6. The method according to claim 1 , further comprising:

providing the conductor layer with second openings for alignment; and

aligning the component with the aid of the second openings when attaching the component to the conductor layer.

7. The method according to claim 1 , further comprising:

providing the conductor layer with at least one third opening for making the at least one via, prior to attaching the component the conductor layer includes openings for making vias.

8. The method according to claim 1 , wherein the base surface includes alignment marks for said alignment of the conductor layer, relative to the base surface.

9. The method according to claim 1 , wherein said attachment of the conductor layer to the base surface comprises;

bringing at least one insulating-material sheet, which is at least partly unhardened, between the base surface and the first surface of the conductor layer.

10. The method according to claim 9 , wherein the at least one insulating-material sheet includes fourth openings made for alignment.

11. The method according to claim 1 , wherein the conductor layer is attached to the base surface with the aid of one insulating material such that the formed insulating-material layer is unified and consists of the single one insulating-material; between the conductor layer and the base surface.

12. The method according to claim 1 , wherein the insulating-material layer between the conductor layer and the base surface is formed after the attachment of the component, and the conductor patterns are formed from the conductor layer after the formation of the insulating-material layer.

13. The method according to claim 1 , wherein the formed insulating material surrounds the component and comes into contact with the surface of the component.

14. The method according to claim 1 , wherein said at least one component comprises a plurality of components in the circuit-board layer, and the method further comprises combining the plurality of components with the aid of the conductor-pattern layer to form an electrically functional totality.

15. The method according to claim 1 , wherein the base surface is a curved surface.

16. The method according to further comprising:

repeating the steps of claim 1 in order to manufacture a second circuit-board layer on top of the first circuit-board layer made on the base surface, wherein the surface of the first circuit-board layer acts as the base surface for the second circuit-board layer.

17. The method according to claim 1 , wherein making the conductive material in the contact openings and making of the at least one via comprises filling the contact openings and at least one via with the conductive material simultaneously using the same process step.

18. The method according to claims 1 , wherein making the at last one via comprises making conductive material using a chemical metallization method and an electrochemical metallization method.

19. The method according to claim 1 , wherein the at least one component comprises at least one microcircuit.

20. The method according to claim 1 , wherein the at least one component comprises contact bumps on the contact areas, the contact bumps forming part of the electrical contacts formed between the contact areas and the conductor layer.

Assignments (9)
CORRECTIVE ASSIGNMENT TO CORRECT THE THE ASSIGNOR NAME PREVIOUSLY RECORDED AT REEL: 052853 FRAME: 0153. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 29, 2021
From: R2 SOLUTIONS LLC
To: STARBOARD VALUE INTERMEDIATE FUND LP, AS COLLATERAL AGENT
Reel/Frame 056832/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED ON REEL 053654 FRAME 0254. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST GRANTED PURSUANT TO THE PATENT SECURITY AGREEMENT PREVIOUSLY RECORDED. Recorded Dec 30, 2020
From: STARBOARD VALUE INTERMEDIATE FUND LP
To: R2 SOLUTIONS LLC
Reel/Frame 054981/0377 →
STATEMENT REGARDING SECURITY INTEREST INCORRECTLY RECORDED AGAINST PATENTS Recorded Oct 20, 2020
From: ACACIA RESEARCH GROUP LLC; R2 SOLUTIONS LLC
To: IMBERATEK, LLC
Reel/Frame 054134/0172 →
RELEASE OF SECURITY INTEREST IN PATENTS Recorded Jul 8, 2020
From: STARBOARD VALUE INTERMEDIATE FUND LP
To: ACACIA RESEARCH GROUP LLC; AMERICAN VEHICULAR SCIENCES LLC; BONUTTI SKELETAL INNOVATIONS LLC; CELLULAR COMMUNICATIONS EQUIPMENT LLC; INNOVATIVE DISPLAY TECHNOLOGIES LLC; LIFEPORT SCIENCES LLC; LIMESTONE MEMORY SYSTEMS LLC; MOBILE ENHANCEMENT SOLUTIONS LLC; MONARCH NETWORKING SOLUTIONS LLC; NEXUS DISPLAY TECHNOLOGIES LLC; PARTHENON UNIFIED MEMORY ARCHITECTURE LLC; R2 SOLUTIONS LLC; SAINT LAWRENCE COMMUNICATIONS LLC; STINGRAY IP SOLUTIONS LLC; SUPER INTERCONNECT TECHNOLOGIES LLC; TELECONFERENCE SYSTEMS LLC; UNIFICATION TECHNOLOGIES LLC
Reel/Frame 053654/0254 →
PATENT SECURITY AGREEMENT Recorded Jun 5, 2020
From: ACACIA RESEARCH GROUP LLC; AMERICAN VEHICULAR SCIENCES LLC; BONUTTI SKELETAL INNOVATIONS LLC; CELLULAR COMMUNICATIONS EQUIPMENT LLC; INNOVATIVE DISPLAY TECHNOLOGIES LLC; LIFEPORT SCIENCES LLC; LIMESTONE MEMORY SYSTEMS LLC; MERTON ACQUISITION HOLDCO LLC; MOBILE ENHANCEMENT SOLUTIONS LLC; MONARCH NETWORKING SOLUTIONS LLC; NEXUS DISPLAY TECHNOLOGIES LLC; PARTHENON UNIFIED MEMORY ARCHITECTURE LLC; R2 SOLUTIONS LLC; SAINT LAWRENCE COMMUNICATIONS LLC; STINGRAY IP SOLUTIONS LLC; SUPER INTERCONNECT TECHNOLOGIES LLC; TELECONFERENCE SYSTEMS LLC; UNIFICATION TECHNOLOGIES LLC
To: STARBOARD VALUE INTERMEDIATE FUND LP, AS COLLATERAL AGENT
Reel/Frame 052853/0153 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 5, 2020
From: GE EMBEDDED ELECTRONICS OY
To: IMBERATEK, LLC
Reel/Frame 051730/0868 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 9, 2014
From: EPCOS AG
To: GE EMBEDDED ELECTRONICS OY
Reel/Frame 034540/0256 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 31, 2012
From: IMBERA ELECTRONICS OY
To: EPCOS AG
Reel/Frame 027627/0428 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 2, 2007
From: TUOMINEN, RISTO; PALM, PETTERI
To: IMBERA ELECTRONICS OY
Reel/Frame 018874/0136 →