Formation of through-wafer electrical interconnections and other structures using a thin dielectric membrane
View Patent ↗Providing through-wafer interconnections in a semiconductor wafer includes forming a sacrificial membrane in a pre-existing semiconductor wafer, depositing metallization over one side of the wafer so as to cover exposed portions of the sacrificial membrane facing the one side of the wafer, removing exposed portions of the sacrificial membrane facing the other side of the wafer, and depositing metallization over the other side of the wafer so as to contact the previously deposited metallization. Techniques also are disclosed for providing capacitive and other structures using thin metal membranes.
1. A method of providing through-wafer interconnections in a semiconductor wafer having first and second sides, the method comprising:
etching the second side of the wafer to form one or more micro-vias;
providing an etch stop layer over the second side, wherein the etch stop layer covers surfaces in the one or more micro-vias;
etching the first side of the wafer to form a cavity in the wafer to a depth that exposes portions of the etch stop layer on the surfaces of the one or more micro-vias;
depositing metallization over one of the first and second sides of the wafer;
subsequently removing regions of the etch stop layer from areas corresponding to where the one or more micro-vias were etched; and
depositing metallization over the other one of the first and second sides of the wafer so that the metallization deposited over the first side is in contact with the metallization deposited over the second side to form the through-wafer interconnections in areas corresponding to where the one or more micro-vias were etched.
2. The method of claim 1 wherein the semiconductor wafer comprises silicon, and the etch stop layer comprises at least one of silicon dioxide or silicon nitride.
3. The method of claim 1 wherein the semiconductor wafer comprises silicon, and wherein providing an etch stop layer includes thermally growing a silicon dioxide layer.
4. The method of claim 1 wherein a dimension of the cavity is larger than a corresponding dimension of each of the one or more micro-vias.
5. The method of claim 1 wherein the first side of the wafer is etched to a depth so as to expose thin membranes of the etch stop layer in the cavity.
6. The method of claim 1 including etching the first side of the wafer such that a sum of the depth of the cavity and an average depth of the one or more micro-vias exceeds the total thickness of the wafer.
7. The method of claim 1 including providing an isolation layer over surfaces of the semiconductor wafer prior to depositing metallization over the one side of the wafer.
8. The method of claim 1 including:
selectively growing an oxide layer over the first and second sides of the wafer after etching the first side of the wafer to form the cavity, such that portions of the etch stop layer remain exposed in the cavity, and wherein the thickness of the oxide layer is greater than the thickness of the etch stop layer; and
wherein removing regions of the etch stop layer includes using an etchant that etches both the etch stop layer and the oxide layer.
9. The method of claim 8 including thermally growing the oxide layer.
10. The method of claim 8 wherein the oxide layer is at least three times as thick as the etch stop layer.