IP Library Granted Patent US 9,348,730
Granted Patent B2
US 9,348,730 · App. 11/669,776 · Granted May 24, 2016

Firmware ROM patch method

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Quick Facts
Patent No.
US 9,348,730
App. No.
11/669,776
Granted
May 24, 2016
Kind
B2
Abstract

A system in which firmware residing in ROM may be upgraded without re-spinning silicon. A one-bit flag may be assigned for each patchable function representing a firmware upgrade. The first statement of each function may check its associated flag and determine if patch-code should be executed in place of the current function residing in ROM. If the flag is not set, the code may continue executing normally. If the flag is set, a function identifier may be placed into a global memory location, and an assembly language “jump” instruction may be executed, redirecting program control to a specified location in a volatile Scratch Read Only Memory (SROM) where the corresponding patched code may be stored. If more than one function is patched, the global identifier may be used to determine which patched function to execute. Using an assembly language “jump” instruction to redirect control results in the patched function's returning normally to its calling function once it has completed executing.

Claims (40)

1. A method for patching a firmware comprising firmware instructions residing within a non-rewritable memory (NRM) comprised in a system, wherein the firmware instructions provide a plurality of functions of said firmware and are mapped to a first area of program memory in the NRM, the method comprising:

providing a re-writable memory operable to store patching information in a first section within the re-writable memory and overlay the re-writable memory on a second area of the program memory, wherein the patching information comprises a plurality of flags in a packed array of one-bit flags defaulting to a reset state, wherein each flag is associated with a respective a single function of said firmware;

for a subset of functions of the plurality of functions that are required to be patched:

setting each respective flag associated with the respective function of the subset of functions in said first section indicating the function needs to be patched, and writing patching instructions associated with the respective function of the subset of functions into a second section of the re-writable memory;

bypassing setting the flag in said first section if the function associated with the flag is not to be patched; and

executing the plurality of functions in said first area of program memory, wherein each function comprises a first statement which when executed, first checks the respective flag associated with the executing function in said first section of the re-writable memory to determine whether to execute patching instructions associated with the at least one executing function within the second section of the re-writable memory if the respective flag is set, or instructions of the function as originally stored in the first area of program memory if the respective flag is not set.

2. The method of claim 1 , further comprising: setting a flag for each function to be patched and writing associated patching instructions into the second section of the re-writeable memory.

3. The method of claim 1 ,

wherein the firmware instructions include a jump instruction which causes a jump to a third second section of the re-writable memory comprising a patcher function for directing execution to the second section of the re-writeable memory containing the patching instructions of the respective function.

4. The method of claim 3 , further comprising:

wherein the patch instructions include a jump instruction which points back to the firmware instructions in said first area of program memory.

5. The method of claim 4 ,

wherein the re-writeable memory comprises a fourth section which stores interrupt vectors.

6. The method of claim 1 ,

wherein the re-writeable memory comprises a fifth section which stores a patch identifier and wherein patching information further includes replaced interrupt vectors in said fourth section.

7. The method of claim 1 , wherein at least one instruction in the third section of the re-writeable memory is an instruction that receives a function's unique identifier as a global variable to determine which patched function to execute and then jumps to a respective patched function in the second section of the re-writable memory.

8. A method for updating one or more functions wherein each function of the one or more functions is implemented by a set of firmware instructions comprised in program code residing within a first memory area of a read-only memory (ROM), the method comprising:

overlaying a second memory area of the ROM with respective memory of a re-writable memory, the re-writable memory operable to store patching information in a first section within the re-writeable memory, wherein the patching information comprises a plurality of flags in a packed array of one-bit flags defaulting to a reset state, wherein each flag is associated with a respective single function implemented by the set of firmware instructions;

for a subset of functions of the one or more functions that are required to be patched:

setting each respective flag associated with the respective function of the subset of functions in said first section of the re-writable memory, and writing patching instructions associated with the respective function of the subset of functions into a second section of the re-writable memory;

executing a function of the one or more functions in said first memory area, wherein each function comprises a first statement which when executed, first checks the respective flag associated with the executing function in said first section of the re-writeable memory;

executing a jump to a patcher function within the second section of the re-writable memory if the respective flag indicates that the function is patched, wherein the patcher function receives information identifying the function to be patched and jumps to the set of instructions implementing the patch in the second section of the re-writable memory; and

resuming execution of program code in the first memory area of the ROM once the patch has been executed;

executing instructions of the function as originally stored in the first memory area of the ROM if the respective flag is not set.

9. The method of claim 8 , further comprising:

executing the set of firmware instructions, if the flag does not indicate that the function is patched.

10. A system comprising:

a non-writable memory (NRM) configured to store a set of firmware instructions in a first memory area of program memory wherein the set of firmware instructions implement a plurality of functions;

a rewritable memory configured to store:

at least one set of patch instructions for patching an associated function of said firmware in a first section of the rewritable memory; and

a plurality of flags in a packed array of one-bit flags in a second section of the rewritable memory, wherein each flag is associated with a respective single function of the plurality of functions, and each flag indicates whether an associated function is to be executed by an associated set of patch instructions in said first section of the rewritable memory or the set of firmware instructions as stored in the first memory area of the NRM; and

a processing unit configured to:

execute a first portion of the set of firmware instructions of a function in the first memory area of the NRM, wherein instructions of the first portion check the respective flag associated with the executing function;

execute the set of firmware instructions as originally stored in the first memory area of the NRM if the respective flag is not set; and

execute the patch instructions associated with the executing function in the first section of the rewritable memory if the respective flag is set.

11. The system of claim 10 , wherein the processing unit is configured to execute a jump to a patcher function within the rewritable memory if an associated flag indicates that the function is patched, wherein the patcher function receives information identifying the function to be patched and jumps to a set of instructions implementing a patch of the function.

12. The system of claim 10 , wherein the set of instructions include a jump instruction which points back to the firmware instructions in said NRM.

13. The system of claim 10 , wherein the rewriteable memory comprises a section which stores interrupt vectors.

14. The system of claim 13 , wherein the re-writeable memory comprises a fifth section which stores a patch identifier.

15. The system of claim 10 , wherein at least one instruction in the patcher function of the rewriteable memory is an instruction that receives a function's unique identifier as a global variable to determine which patched function to execute and wherein the patcher function then jumps to a respective patched function in the second section of the rewritable memory.

Assignments (10)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
MERGER Recorded Dec 11, 2017
From: STANDARD MICROSYSTEMS CORPORATION
To: MICROCHIP TECHNOLOGY INCORPORATED
Reel/Frame 044824/0608 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 21, 2007
From: ODLIVAK, ANDREW J.; KUMAR, RAVINDRA; STEARNS, WARREN R.; ROCKFORD, JOHN GLEN
To: STANDARD MICROSYSTEMS CORPORATION
Reel/Frame 019040/0652 →