Methods and apparatus for employing redundant arrays to configure non-volatile memory
View Patent ↗Systems, methods and apparatus are disclosed for employing redundant arrays to configure non-volatile memory. The present invention may include a substrate including a plurality of memory arrays, wherein the memory arrays include a data array and at least three redundant configuration arrays. The configuration arrays may each be adapted to be programmed with identical configuration information associated with operation of the data array. Majority voting logic with an output coupled to configuration inputs of the data array and inputs coupled to each of the redundant configuration arrays may be employed. The majority voting logic may be adapted to determine a configuration for the data array based upon an outcome of a majority vote function applied to the configuration information stored in the configuration arrays. Numerous other aspects are disclosed.
1. A memory comprising:
a plurality of memory arrays, wherein the memory arrays include:
a data array;
at least three redundant configuration arrays, wherein the configuration arrays are each adapted to be programmed with identical configuration information associated with operation of the data array, and wherein the configuration arrays are disposed on different substrates; and
dissent detection logic coupled to each of the configuration arrays.
2. The memory of claim 1 wherein the data array includes support logic and the configuration information is associated with operation of the support logic.
3. The memory of claim 1 , further comprising logic coupled between the data array and each of the configuration arrays, wherein the logic is adapted to determine a configuration for the data array based upon an outcome of a majority vote function applied to the configuration information stored in the configuration arrays.
4. The memory of claim 1 wherein the data array includes a plurality of non-volatile memory cells.
5. The memory of claim 1 wherein the data array includes a plurality of two-terminal memory cells.
6. The memory of claim 1 wherein the data array includes at least one of flash memory, NAND flash memory, electrically erasable programmable memory, ultraviolet erasable programmable memory, magnetic memory, one time programmable memory, ferroelectric RAM, and carbon nano-tube based memory.
7. The memory of claim 1 wherein the configuration information defines a logical structure of the data array.
8. The memory of claim 1 wherein the configuration information includes at least one of trimbit values, reference voltage values, and mode selection values.
9. The memory of claim 1 wherein the configuration arrays each include a plurality of non-volatile memory cells.
10. The memory of claim 1 wherein the configuration arrays each include a plurality of two-terminal memory cells.
11. The memory of claim 1 wherein the configuration arrays each include at least one of fuse based memory and antifuse based memory.
12. The memory of claim 1 wherein the configuration arrays are distributed on the substrate.
13. The memory of claim 1 where the configuration arrays are distributed on the substrate based upon at least one requirement of signal timing, substrate stress, reliability, and yield.
14. The memory of claim 1 wherein the number of configuration arrays included on the substrate is based on a reliability threshold.
15. The memory of claim 1 wherein the configuration arrays include error-correcting code (ECC) memory.
16. The memory of claim 1 , further comprising majority vote logic coupled to each of the configuration arrays and adapted to determine a reliability rating of the configuration information stored in the configuration arrays.
17. A memory comprising:
a plurality of memory arrays including a primary array and a plurality of configuration arrays,
wherein the configuration arrays are each adapted to store redundant configuration information associated with operation of the primary array, and
wherein the configuration arrays are disposed on different substrates.
18. The memory of claim 17 wherein the primary array includes support logic and the configuration information is associated with operation of the support logic.