High-speed digital multiplexer
View Patent ↗A high-speed digital multiplexer is disclosed, The multiplexer includes a plurality of input pins for receiving a plurality of digital input signals ad switching circuitry coupled to the input pins. The switching circuitry has respective outputs coupled to a common node and is operative to enable a selected one of the plurality of input pins, The multiplexer further includes a local signal converter having a circuit branch set to a common voltage. The branch is connected to the common node to sense changes in current corresponding to an input signal received by an enabled input pin. An output pin is coupled to the local signal converter, whereby the local signal converter is operative to produce voltage changes at the output corresponding to the sensed current changes.
1. A method of selecting one from a plurality of input signals applied to a plurality of input pins, the input pins coupled through switching circuitry to a common node, the method comprising the steps:
applying a constant voltage to the common node;
activating one pin of the plurality of input pins corresponding to a selected one of the plurality of input signals;
maintaining a reverse-bias condition at diodes corresponding to non-selected ones of the plurality of input signals;
detecting current changes at the common node caused by the selected one of the plurality of input signals; and
producing output voltage changes corresponding to the detected current changes,
wherein the produced output voltage comprises falling and rising edges corresponding to delayed edges of the input signal.
2. A method according to claim 1 , wherein the step of activating comprises:
driving each non-selected one of the plurality of input signals to a voltage higher than the common voltage; and
driving the selected one of the plurality of input signals to a voltage lower than the common voltage.
3. The method of claim 1 , wherein the plurality of input signals comprise a plurality of digital signals.
4. The method of claim 3 , wherein the digital signals are high-speed digital signals.
5. The method of claim 1 , wherein activating the one pin of the plurality of input pins comprises applying a signal pulse to the one pin of the plurality of input pins.
6. The method of claim 1 , further comprising driving the selected one of the plurality of input signals to a voltage higher than a tester signal logic “one” and lower than the logical “high” voltage, Vh.
7. The method of claim 1 , further comprising receiving at each one of the plurality of input pins, an input signal from a respective channel.
8. A method of selecting one from a plurality of input signals applied to a plurality of input pins, the input pins coupled through switching circuitry to a common node, the method comprising the steps:
applying a constant voltage to the common node;
activating one pin of the plurality of input pins corresponding to a selected one of the plurality of input signals;
maintaining a reverse-bias condition at diodes corresponding to non-selected ones of the plurality of input signals;
detecting current changes at the common node caused by the selected one of the plurality of input signals;
producing output voltage changes corresponding to the detected current changes;
receiving at each one of the plurality of input pins, an input signal from a respective channel; and
impedance matching each one of the plurality of input pins to the respective channel.
9. The method of claim 8 , where in the impedance is matched to 50 Ohms.
10. The method of claim 1 , wherein the selected one of the plurality of input signal is shorted to an “AC” ground.
11. The method of claim 1 , further comprising calibrating to correct for the delay.
12. A method of selecting one from a plurality of input signals applied to a plurality of input pins, the input pins coupled through switching circuitry to a common node, the method comprising the steps:
applying a constant voltage to the common node;
activating one pin of the plurality of input pins corresponding to a selected one of the plurality of input signals;
maintaining a reverse-bias condition at diodes corresponding to non-selected ones of the plurality of input signals;
detecting current changes at the common node caused by the selected one of the plurality of input signals; and
producing output voltage changes corresponding to the detected current changes,
wherein producing output voltage changes corresponding to the detected current changes is accomplished using a current-controlled voltage source.
13. The method of claim 12 , wherein the current-controlled voltage source comprises a transresistance amplifier.
14. The method of claim 1 , wherein maintaining a reverse-bias condition at diodes corresponding to non-selected ones of the plurality of input signals comprises applying a logical “high” voltage, Vh, to a cathode terminal of each of the diodes.
15. A high-speed digital multiplexer comprising:
a plurality of input pins;
switching circuitry;
a common node coupled to the input pins through the switching circuitry;
means for applying a constant voltage to the common node;
means for activating one pin of the plurality of input pins corresponding to a selected one of the plurality of input signals;
means for maintaining a reverse-bias condition at diodes corresponding to non-selected ones of the plurality of input signals and for maintaining a forward-bias condition at a diode corresponding to the selected one of the plurality of input signals;
means for detecting current changes at the common node caused by the selected one of the plurality of input signals; and
means for producing output voltage changes corresponding to the detected current changes.