Overdrive write method, write amplifier power generating circuit, and semiconductor memory device including the same
View Patent ↗A write amplifier power generating circuit includes a control unit for changing an output voltage. In a first write cycle in which a pair of bit lines are being amplified, a write operation is performed by an overdrive write method in which a high level from a write amplifier is set to a first voltage (for example, a power supply voltage). In a second write cycle after amplification in the pair of the bit lines has been completed, a write operation is performed by a write method in which the high level from the write amplifier is set to a second voltage (for example, an internal voltage).
1. A semiconductor memory device comprising:
a write amplifier power generating circuit that supplies, as a power supply voltage of a write amplifier, a first voltage in a first write cycle in which a write overdrive signal is activated and a second voltage in a second write cycle in which the write overdrive signal is deactivated,
wherein the second voltage is a high level voltage to be written to a memory cell, and the first voltage is higher than the second voltage and, wherein the write overdrive signal is activated by activating a RAS-TIME-OUT signal and a write enable signal and deactivated by deactivating the RAS-TIME-OUT signal.
2. The semiconductor memory device according to claim 1 , wherein the write overdrive signal is activated by activating a write enable signal and deactivated by the time amplification in a pair of bit lines that are amplified according to data stored in a memory cell is completed.
3. The semiconductor memory device according to claim 1 , wherein the write overdrive signal is activated by activating a sense overdrive signal and a write enable signal and deactivated by deactivating the sense overdrive signal.
4. The semiconductor memory device according to claim 1 , wherein the write amplifier power generating circuit includes current mirror transistors, differential input transistors to which a reference voltage and an output voltage are individually input, and a driver transistor, and voltages of gates of the current mirror transistors and the driver transistor are controlled.
5. The semiconductor memory device according to claim 4 , wherein the write amplifier power generating circuit further includes a regulator transistor connected in parallel with one of the differential input transistors to which the reference voltage is input, and a second reference voltage is input to a gate of the regulator transistor.
6. The semiconductor memory device according to claim 5 , wherein the write amplifier power generating circuit further includes a connection control transistor connected in series with the regulator transistor, and a connection control signal is input to a gate of the connection control transistor.
7. An overdrive write method in which, in individual write cycles, a write high level from a write amplifier is changed depending on a status of a pair of bit lines that are amplified according to data stored in a memory cell,
wherein the write high level is set to a first voltage in a first write cycle in which the pair of the bit lines are being amplified and is set to a second voltage in a second write cycle after amplification in the pair of the bit lines has been completed,
wherein the second voltage is a high level voltage to be written to a memory cell, and the first voltage is higher than the second voltage and,
wherein switching from the first write cycle to the second write cycle is performed according to a RAS-TIME-OUT signal.
8. The overdrive write method according to claim 7 , wherein switching from the first write cycle to the second write cycle is performed in synchronization with deactivation of a sense overdrive signal.
9. A semiconductor memory device that performs a write operation by the overdrive write method according to claim 8 or 7 .
10. A semiconductor memory device comprising:
a memory cell;
a bit line connected with the memory cell;
a sense amplifier that operates on a first operating voltage during a first period of time to amplify a potential of the bit line and on a second operating voltage during a second period of time to further amplify the potential of the bit line, the second period of the time following the first period of time, the first operating voltage being larger in absolute value than the second operating voltage; and
a write amplifier that responds to a data to be written into the cell to supply the bit line with a first writing voltage during a third period of time and with a second writing voltage during a fourth period of time, the first writing voltage being larger in absolute value than the second writing voltage, the third period of time being included in the first period of time, the fourth period of time being included in the second period time.
11. The semiconductor memory device according to claim 10 , wherein the write amplifier is connected with the bit line via a transfer switch.
12. The semiconductor memory device according to claim 10 , wherein the first operating voltage is the same as the first writing voltage and the second operating voltage is the same as the second writing voltage.
13. The semiconductor memory device according to claim 10 , further comprising a write amplifier power generating circuit that supplies the write amplifier with the first writing voltage during the first period of time and with the second writing voltage during the second period of time.