Internal power supply generating circuit without a dead band
View Patent ↗An internal power supply generating circuit has a control circuit for controlling a control node voltage of a driver circuit thereof. During an overdrive duration, the control node voltage is set at an appropriate level of an operation range by controlling the control node voltage by the control circuit. By setting the control node voltage at the appropriate level, the internal power supply generating circuit can supply an internal power-supply voltage without a dead band after the overdrive duration. With this structure, the internal power supply generating circuit without the dead band can be obtained and a semiconductor device operable at a high speed comprising the internal power supply generating circuit can be obtained.
1. An internal power supply generating circuit for generating an internal power-supply voltage from an external power-supply voltage, comprising:
a current mirror circuit having an external input terminal supplied with the external power-supply voltage, said current mirror circuit having a pair of mirror output nodes;
a differential amplifying circuit connected to the pair of mirror output terminals, said differential amplifying portion having a reference input terminal supplied with a reference voltage and an internal output terminal for producing the internal power-supply voltage;
a driver circuit connected between the external input terminal and the internal output terminal, said driver circuit having a driver control node connected to said current mirror circuit; and
a control circuit, connected to the driver control node, for controlling variations of a voltage at the driver control node.
2. The internal power supply generating circuit as claimed in claim 1 , said differential amplifying circuit comprising a reference differential transistor having a gate connected to the reference input terminal and a feedback differential transistor having a gate connected to the internal output terminal, wherein said control circuit comprises a regulator transistor connected in parallel with the feedback differential transistor.
3. The internal power supply generating circuit as claimed in claim 2 , wherein said regulator transistor has a gate supplied with an additional reference voltage.
4. The internal power supply generating circuit as claimed in claim 3 , wherein said variations of the voltage at the driver control node is caused by an overdrive voltage from an output side, said additional reference voltage being equal to the reference voltage for an overdrive duration.
5. The internal power supply generating circuit as claimed in claim 3 , wherein said variations of the voltage at the driver control node is caused by an overdrive voltage from an output side, said additional reference voltage being lower than the reference voltage for an overdrive duration.
6. The internal power supply generating circuit as claimed in claim 5 , wherein said additional reference voltage is equal to a ground voltage for the overdrive duration.
7. The internal power supply generating circuit as claimed in claim 3 , wherein said additional reference voltage is equal to the external power-supply voltage.
8. The internal power supply generating circuit as claimed in claim 1 , wherein said control circuit comprises a logic circuit connected to said driver control node, said logic circuit setting said driver control node within an operation range of said driver circuit at a time when an overdrive comes to an end.
9. The internal power supply generating circuit as claimed in claim 8 , wherein said control circuit does not supply said current mirror circuit with the external power-supply voltage for an overdrive duration.
10. The internal power supply generating circuit as claimed in claim 8 , said differential amplifying circuit comprising a reference differential transistor having a gate connected to the reference input terminal and a feedback differential transistor having a gate connected to the internal output terminal, wherein said internal power supply generating circuit further comprises a regulator transistor connected in parallel with the reference differential transistor.
11. The internal power supply generating circuit as claimed in claim 10 , wherein said regulator transistor has a gate supplied with an additional reference voltage.
12. A semiconductor memory device comprising:
a plurality of memory cell arrays each of which comprises a plurality of memory cells in a matrix fashion, each memory cell array having a plurality of bit line pairs and a plurality of word lines;
a plurality of sense amplifier rows each of which comprises a plurality of sense amplifiers connected to the plurality of bit line pairs;
a plurality of word line columns each of which comprises a plurality of word drivers for driving the plurality of word lines;
an internal power supply generating circuit for generating an internal power-supply voltage from an external power-supply voltage; and
a sense amplifier power supply circuit connected to the sense amplifier rows and to said internal power supply generating circuit, said sense amplifier power supply circuit supplying, as an overdrive voltage, the external power-supply voltage to the sense amplifier rows for an overdrive duration, said sense amplifier power supply circuit supplying the internal power-supply voltage to the sense amplifier rows after the overdrive duration,
wherein said internal power supply generating circuit comprises:
a current mirror circuit having an external input terminal supplied with the external power-supply voltage, said current mirror circuit having a pair of mirror output nodes;
a differential amplifying circuit connected to the pair of mirror output terminals, said differential amplifying portion having a reference input terminal supplied with a reference voltage and an internal output terminal for producing the internal power-supply voltage;
a driver circuit connected between the external input terminal and the internal output terminal, said driver circuit having a driver control node connected to said current mirror circuit; and
a control circuit, connected to the driver control node, for controlling variations of a voltage at the driver control node.
13. The semiconductor memory device as claimed in claim 12 , said differential amplifying circuit comprising a reference differential transistor having a gate connected to the reference input terminal and a feedback differential transistor having a gate connected to the internal output terminal, wherein said control circuit comprises a regulator transistor connected in parallel with the feedback differential transistor.
14. The semiconductor memory device as claimed in claim 13 , wherein said regulator transistor has a gate supplied with an additional reference voltage.
15. The semiconductor memory device as claimed in claim 14 , wherein said variations of the voltage at the driver control node is caused by the overdrive voltage from an output side, said additional reference voltage being equal to the reference voltage for the overdrive duration.
16. The semiconductor memory device as claimed in claim 14 , wherein said variations of the voltage at the driver control node is caused by the overdrive voltage from an output side, said additional reference voltage being lower than the reference voltage for the overdrive duration.
17. The semiconductor memory device as claimed in claim 16 , wherein said additional reference voltage is equal to a ground voltage for the overdrive duration.
18. The semiconductor memory device as claimed in claim 12 , wherein said control circuit comprises a logic circuit connected to said driver control node, said logic circuit setting said driver control node within an operation range of said driver circuit after the completion of the overdrive duration.
19. The semiconductor memory device as claimed in claim 18 , wherein said control circuit does not supply said current mirror circuit with the external power-supply voltage for the overdrive duration.
20. The semiconductor memory device as claimed in claim 18 , said differential amplifying circuit comprising a reference differential transistor having a gate connected to the reference input terminal and a feedback differential transistor having a gate connected to the internal output terminal, wherein said internal power supply generating circuit further comprises a regulator transistor connected in parallel with the reference differential transistor.
21. The semiconductor memory device as claimed in claim 20 , wherein said regulator transistor has a gate supplied with an additional reference voltage.