System and method for IM3 reduction and cancellation in amplifiers
View Patent ↗Sets of power amplifier branches (which comprise an RF/microwave amplifier stage) are power combined within each stage and each set of power amplifier branches are biased in different classes of operation by bias circuits possessing different impedance characteristics such that the fundamental frequency components present at the output are in-phase with one another and the IMD3 components are anti-phase over a broad range of power levels. The RF input signal is provided by the output of the previous stage of the RF/microwave amplifier. The output of each stage is formed by power combining sets of these power amplifier branches, each of which are separately biased, so the fundamental components are additive resulting in the maximum possible output power and the IM3 components cancel partially or completely. IM3 reduction or cancellation can be achieved over a large range of output powers with the use of a feed forward control loop monitoring the input power and appropriately adjusting the bias currents and impedance characteristics of the bias circuits feeding the individual power amplifier branches in each stage of the RF/microwave amplifier.
1. A discrete amplifier for canceling at least one distortion component at the output of the discrete amplifier comprising:
a. a first stage having at least a first branch and a second branch in parallel with one another, wherein each of said first and second branches is formed of one or more transistor legs having one or more unit cells in parallel with one another;
b. a second stage having at least a third branch and a fourth branch in parallel with one another, wherein each of said third and fourth branches is formed of one or more transistor legs having one or more unit cells in parallel with one another;
c. a first biasing circuit having a first impedance and a first biasing level, said first biasing circuit being operatively connected to said first stage first branch for biasing said first branch into a first mode of operation;
d. a second biasing circuit having a second impedance and a second biasing level, said second biasing circuit being operatively connected to said first stage second branch for biasing said second branch into a second mode of operation;
e. a third biasing circuit having a third impedance and a third biasing level, said third biasing circuit being operatively connected to said second stage third branch for biasing said third branch into a third mode of operation;
f. a fourth biasing circuit having a fourth impedance and a fourth biasing level, said fourth biasing circuit being operatively connected to said second stage fourth branch for biasing said fourth branch into a fourth mode of operation, wherein at least one of
a. said first mode of operation and said second mode of operation, and
b. said third mode of operation and said fourth mode of operation are chosen so that at least one distortion component is substantially canceled at a respective output of at least one of said first stage and said second stage.
2. The discrete amplifier of claim 1 , wherein said first biasing circuit first impedance and first biasing level differs from said second biasing circuit second impedance and second biasing level.
3. The discrete amplifier of claim 1 , wherein
a. said impedance of said first and second biasing circuits and said biasing level of said first and second branches are different from one another, and
b. said impedance of said third and fourth biasing circuits and said biasing level of said third and fourth branches are different from one another,
and chosen so as to maximize the cancellation of said at least one distortion component at the output of at least one of said first stage and said second stage of said discrete amplifier.
4. The discrete amplifier of claim 1 , wherein said first, said second, said third and said fourth branches are formed on a single integrated circuit chip and said first biasing circuit, said second biasing circuit, said third biasing circuit and said fourth biasing circuit are physically located on said same single integrated circuit chip to minimize electrical parasitics so as to maximize the cancellation of said at least one distortion component.
5. The discrete amplifier of claim 1 , further comprising a sensing circuit that senses the input power to said discrete amplifier and causes at least one of said first, said second, said third and said fourth biasing circuits to adjust the operating mode of its respective branch by adjusting at least one of said biasing circuit level and impedance so as to maximize the cancellation of said at least one distortion component.
6. The discrete amplifier of claim 1 , wherein said first mode, said second mode, said third mode and said fourth mode are chosen from one of Class A, Class B, Class C, and Class AB modes of operation.
7. The discrete amplifier of claim 6 , wherein said first, said second, said third and said fourth biasing circuits are adjusted to change the impedance of said respective biasing circuits to maximize the cancellation of said at least one distortion component.
8. The discrete amplifier of claim 6 , wherein said first branch first mode and said second branch second mode cause a substantial cancellation of at least one harmonic.
9. The discrete amplifier of claim 6 , wherein said third branch third mode and said fourth branch fourth mode cause a substantial cancellation of a third order inter-modulation distortion component.
10. The discrete amplifier of claim 6 , wherein one of said first stage first branch and said first stage second branch have a plurality of transistor legs to increase the output power of said one of said first stage first branch and said first stage second branch.
11. A discrete amplifier for canceling at least one distortion component at the output of the discrete amplifier comprising:
a. an input port for receiving a first signal;
b. an output port for outputting a second signal that is related to said first signal;
c. a first branch operatively connected to said input and said output ports and a second branch in parallel with said first branch and operatively connected to said input and said output ports,
d. a first biasing circuit operatively connected to said first branch for biasing said first branch into a first mode of operation;
e. a second biasing circuit operatively connected to said second branch for biasing said second branch into a second mode of operation;
f. a sensing circuit that senses said first signal and causes at least one of said first and said second biasing circuits to change the operating mode of its respective branch by adjusting at least one of a biasing circuit current and impedance so as to maximize the cancellation of said at least one distortion component,
wherein said first mode of operation and said second mode of operation are chosen so that said at least one distortion component in said second signal is substantially reduced.
12. The circuit of claim 11 , wherein said first and said second branches are formed on a single integrated circuit chip and said first and said second biasing circuit are physically located on said same single integrated circuit chip to minimize electrical parasitics so as to maximize the cancellation of said at least one distortion component.
13. The discrete amplifier of claim 11 , wherein said at least one distortion component is a third harmonic of said first signal.
14. The discrete amplifier of claim 11 , wherein said mode of operation is chosen from one of Class A, Class B, Class C, and Class AB modes of operation.
15. A circuit for canceling at least one distortion component at the output of the circuit comprising:
a. a power splitter having
i. a first input port,
ii. a first output port, and
iii. a second output port;
wherein a first signal is input on said power splitter first input port and is split into a second signal at said power splitter first output port and a third signal at said power splitter second output port;
b. a power combiner having
i. a first input port,
ii. a second input port, and
iii. a first output port,
c. a first amplifier having
i. an input port coupled to said power splitter first output port, and
ii. an output port coupled to said power combiner first input port;
d. a second amplifier in parallel with said first amplifier, said second amplifier having
i. an input port coupled to said power splitter second output port, and
ii. an output port coupled to said power combiner second input port;
e. at least one biasing circuit operatively connected with one of said first and said second amplifiers for biasing said one of said first and said second amplifiers in a different class of operation than the other of said first and said second amplifiers; and
f. at least one control logic circuit for sensing said first signal and for causing at least one of
i. a size of said one of said first and said second amplifiers to change based on said first signal, and
ii. a magnitude of a biasing level of said one of said first and said second amplifiers to change based on said first signal,
wherein a fourth signal is output from said power combiner first output port having at least one distortion component reduced.
16. The circuit of claim 15 , further comprising a second biasing circuit operatively connected to said other of said first and said second amplifiers for biasing said other of said first and said second amplifiers into a class of operation different than said one of said first and said second amplifiers so that said at least one distortion component is reduced in said fourth signal.
17. The circuit of claim 15 , wherein said at least one distortion component is a third harmonic of said first signal.
18. The circuit of claim 15 , wherein said at least one distortion component is a third order inter-modulation product of said first signal.
19. The circuit of claim 15 , wherein said modes of operation are chosen from one of Class A, Class B, Class C, and Class AB modes of operation.
20. The circuit of claim 15 , wherein said power splitter and said power combiner are quadrature hybrids.
21. A discrete amplifier for canceling at least one distortion component at the output of the discrete amplifier comprising:
a. a first stage having at least a first branch and a second branch in parallel with one another;
b. a second stage having at least a third branch and a fourth branch in parallel with one another;
c. a first biasing circuit operatively coupled to said first stage first branch, said first biasing circuit being configured to provide a first impedance and a first biasing level that drives said first branch into a first mode of operation;
d. a second biasing circuit operatively coupled to said first stage second branch, said second biasing circuit being configured to provide a second impedance and a second biasing level that drives said second branch into a second mode of operation that is different from said first mode of operation;
e. a third biasing circuit operatively coupled to said second stage third branch, said third biasing circuit being configured to provide a third impedance and a third biasing level that drives said third branch into a third mode of operation;
f. a fourth biasing circuit operatively coupled to said second stage fourth branch, said fourth biasing circuit being configured to provide a fourth impedance and a fourth biasing level that drives said fourth branch into a fourth mode of operation that is different from said third mode of operation,
wherein
said first and said second bias circuit impedances at baseband frequencies are different,
said third and fourth bias circuit impedances at baseband frequencies are different, and
are chosen so that at least one distortion component is substantially cancelled at a respective output of at least one of said first stage and said second stage.