TEST STRUCTURES AND METHODS FOR INSPECTION OF SEMICONDUCTOR INTEGRATED CIRCUITS
Disclosed is a semiconductor die having a scanning area. The semiconductor die includes a first plurality of test structures wherein each of the test structures in the first plurality of test structures is located entirely within the scanning area. The semiconductor die further includes a second plurality of test structures wherein each of the test structures in the first plurality of test structures is located only partially within the scanning area. The test structures are arranged so that a scan of the scanning area results in detection of defects outside of the scanning area.
1 . A semiconductor die having a scanning area, the semiconductor die comprising:
a first plurality of test structures wherein each of the test structures in the first plurality of test structures is located entirely within the scanning area;
a second plurality of test structures wherein each of the test structures in the first plurality of test structures is located only partially within the scanning area,
wherein the test structures are arranged so that a scan of the scanning area results in detection of defects outside of the scanning area.
2 . The semiconductor die of claim 1 wherein the first plurality of test structures comprises test structures that are electrically isolated and others that are not.
3 . The semiconductor die of claim 1 wherein the second plurality of test structures comprises test structures that are electrically isolated and others that are not.
4 . The semiconductor die of claim 1 the first plurality of test structures comprises test structures that are electrically isolated and others that are not and the second plurality of test structures comprises test structures that are electrically isolated and others that are not.
5 . The semiconductor die of claim 1 wherein the second plurality of test structures comprises test structures that are primarily located outside the scanning area.
6 . A semiconductor die as recited in claim 5 wherein the second plurality of test structures are arranged such that a short associated with a portion of the second plurality of test structures that is located outside the scanning area is detectable by performing voltage contrast on a portion of the second plurality of test structures that is located within the scanning area.
7 . The semiconductor die of claim 1 wherein product circuitry resides on the semiconductor die outside of the primary scan area.
8 . The semiconductor die of claim 1 wherein the scanning area is located in the middle of semiconductor die.
9 . A wafer having a plurality semiconductor dies as recited in claim 1 .
10 . A wafer as recited in claim 9 , wherein at least two of the scanning areas from two of the semiconductor dies are aligned along their longitudinal axis.
11 . The semiconductor die of claim 1 , wherein the semiconductor die has a plurality of scanning areas.
12 . The semiconductor die of claim 1 , wherein the second plurality of test structures form a rectangular shape and the scanning areas are arranged to optimize an aspect ratio of the second plurality of test structures of each scanning area.
13 . The semiconductor die of claim 1 , wherein the scanning areas are arranged in a checkerboard pattern.
14 . The semiconductor die of claim 1 , wherein the first plurality of test structures include a mix of test structure types.
15 . The semiconductor die of claim 11 wherein the first plurality of test structures include a first type of test structure and a second type of test structure, the first type differing from the second type, and the first and second test structures are selected from a group consisting of a via chain test structure, a chemical mechanical polishing (CMP) test structure, a contact array test structure, a test structure for measuring misalignment, and a CMP dummy metal filler test structure.
16 . The semiconductor die of claim 15 , wherein the CMP test structure is arranged for measurement of a CMP parameter selected from a group consisting of a pitch value, a density value, and a horizontal aspect ratio value.
17 . The semiconductor die of claim 1 , wherein the first plurality of test structures for a contiguous single structure that is coupled to a predefined voltage potential and the second plurality of test structures form a plurality of separate lines interleaved between portions of the first test structures.
18 . The semiconductor die of claim 17 , wherein the first test structures form a serpentine shaped structure and includes one or more contacts that are coupled to the predefined voltage potential.
19 . The semiconductor die of claim 18 , wherein the one or more contacts are located within the middle of the first test structures and is coupled to a ground potential, the second test structures being designed to be floating.
20 . A semiconductor die comprising a scanning area having a plurality of test structures located entirely within the scanning area, wherein the test structures include a first type of test structure and a second type of test structure, the first type differing from the second type.
21 . The semiconductor die of claim 20 , wherein the first type of test structures and the second type of test structures are selected from a group consisting of a via chain test structure, a chemical mechanical polishing (CMP) test structure, a contact array test structure, a test structure for measuring misalignment, and a CMP dummy metal filler test structure.
22 . The semiconductor die of claim 21 , wherein the CMP test structure is arranged for measurement of a CMP parameter selected from a group consisting of a pitch value, a density value, and a horizontal aspect ratio value.
23 . The semiconductor die of claim 20 , wherein the test structures include multiple test structures of the first type and multiple test structures of the second type.
24 . A semiconductor die comprising at least one electrically isolated conductive test structure positioned adjacent to at least one electrically non-isolated conductive test structures, wherein a first portion of the at least one electrically isolated test structure is located within a scanning area and a second portion of the at least one electrically isolated test structure is located outside the scanning area so that a short between the second portion of the at least one electrically isolated test structure and the at least one electrically non-isolated test structure is detectable through voltage contrast on the first portion of the at least one electrically isolated test structure.
25 . A semiconductor as recited in claim 24 , wherein the electrically isolated test structure is formed from a same conductive layer as the electrically non-isolated test structure.
26 . A semiconductor as recited in claim 24 , wherein the electrically isolated test structure is formed from a different conductive layer as the electrically non-isolated test structure.
27 . A semiconductor as recited in claim 21 , wherein a width of the first portion of the at least one electrically non-isolated test structure is substantially equal to or less than a width of the second portion.
28 . A semiconductor die comprising at least one electrically non-isolated conductive test structure, wherein a first portion of the at least one electrically non-isolated test structure is located within a scanning area and a second portion of the at least one electrically non-isolated test structure is located outside the scanning area so that an open type defect within the at least one electrically non-isolated test structure is detectable through voltage contrast on the first portion of the at least one electrically isolated test structure and wherein a width of the first portion of the at least one electrically non-isolated test structure is substantially equal to or less than a width of the second portion.
29 . A method of forming a semiconductor die comprising a scanning area, the method comprising:
forming a plurality of test structures located entirely within the scanning area, wherein the test structures include a first type of test structure and a second type of test structure, the first type differing from the second type.
30 . The method of claim 29 , wherein the first type of test structures and the second type of test structures are selected from a group consisting of a via chain test structure, a chemical mechanical polishing (CMP) test structure, a contact array test structure, a test structure for measuring misalignment, and a CMP dummy metal filler test structure.
31 . The method of claim 30 , wherein the CMP test structure is arranged for measurement of a CMP parameter selected from a group consisting of a pitch value, a density value, and a horizontal aspect ratio value.
32 . The method of claim 29 , wherein the test structures include multiple test structures of the first type and multiple test structures of the second type.