Multiple port memory with prioritized world line driver and method thereof
View Patent ↗A multiple port memory has a word line driver that provides a word line signal to access a first write port of a multiple port memory cell in an array of multiple port memory cells during a write operation. A first logic circuit has a first input for receiving a first port selection signal, a second input for receiving a disable signal, and an output. A buffer circuit has an input coupled to the output of the first logic circuit, and an output for providing the word line signal. The disable signal is asserted to prevent the word line driver from accessing the first write port when a second write port of the multiple port memory cell is accessed during the write operation and the second write port has a higher priority than the first write port.
1. A multiple port memory comprising a word line driver for providing a first word line signal to access a first write port of a multiple port memory cell in an array of multiple port memory cells during a write operation and a second word line signal to access a second write port, the word line driver comprising:
a first logic circuit comprising a first logic gate having a first input for receiving a clocked first port selection signal, a second input for receiving a disable signal, and an output coupled to the first write port and comprising a second logic gate having an output connected to the second input of the first logic gate for providing the disable signal and to a second write port of the multiple port memory cell, the second logic gate having an input for receiving a clocked second port selection signal during the write operation that accesses the second write port and disables access to the first write port thereby establishing a higher priority to access the second write port than the first write port;
a first buffer circuit having an input coupled to the output of the first logic gate, and an output for providing the first word line signal; and
a second buffer circuit having an input coupled to the output of the second logic gate, and an output for providing the second word line signal;
wherein the disable signal is asserted to prevent the word line driver from accessing the first write port when the second write port of the multiple port memory cell is accessed during the write operation and the second write port has a higher priority than the first write port.
2. The multiple port memory of claim 1 , wherein the first logic gate is a logic NAND and the second logic gate is a logic NAND.
3. The multiple port memory of claim 2 , wherein the first buffer circuit is a first inverter and the second buffer circuit is a second inverter.
4. The multiple port memory of claim 3 , wherein the at least one port selection signal is received from a row address predecoder circuit.
5. The multiple port memory of claim 1 , wherein the first logic gate comprises an AND-OR-INVERT logic function and the second logic gate comprises an AND-OR-INVERT logic function.
6. The multiple port memory of claim 1 , wherein the multiple port memory cell comprises first and second storage nodes coupled to a pair of cross-coupled inverters, the first and second storage nodes coupled to a first bit line pair in response to the first word line signal, and the first and second storage nodes coupled to a second bit line pair in response to the second word line signal.
7. The multiple port memory of claim 1 , further comprising:
an address predecode circuit for receiving a plurality of write port addresses and providing predecoded addresses to the word line driver; and
a dynamic priority selector circuit coupled to the address predecode circuit for determining which of the first and second write ports has a higher priority in response to a user input.
8. A multiple port memory comprising:
a memory cell array having a plurality of multiple port memory cells, a multiple port memory cell of the plurality of multiple port memory cells coupled to at least two write word lines; and
a plurality of word line drivers, each of the plurality of word line drivers for providing a word line signal to access a predetermined port of a predetermined memory cell of the plurality of multiple port memory cells, each of the plurality of word line drivers comprising:
a first logic circuit having a first input for receiving a first port selection signal, a second input for receiving a disable signal, a third input for receiving a clock signal which is a write signal for enabling write operation in the multiple port, and an output; and
a buffer circuit having an input coupled to the output of the first logic circuit, and an output for providing the word line signal;
wherein the disable signal is asserted to prevent the word line driver from accessing the first write port when a second write port of the multiple port memory cell is accessed during a write operation and the second write port has a higher priority than the first write port.
9. The multiple port memory of claim 8 , further comprising a disable circuit having an input coupled to receive a second port selection signal, and an output coupled to the second input of the first logic circuit to provide the disable signal.
10. The multiple port memory of claim 9 , wherein the disable circuit comprises a logic gate having an input for receiving the second port selection signal, and an output for providing the disable signal.
11. The multiple port memory of claim 10 , further comprising a row address predecoder circuit for providing the first and second port selection signals.
12. The multiple port memory of claim 10 , wherein the logic gate comprises one of either a NAND logic function or an AND-OR-INVERT logic function.
13. The multiple port memory of claim 8 , wherein the memory cell away is implemented as one of either a register file or a random access memory in a data processing system, the data processing system further comprising:
a bus; and
a plurality of bus masters coupled to the bus.
14. The multiple port memory of claim 8 , further comprising:
an address predecode circuit for receiving a plurality of write port addresses and providing predecoded addresses to the word line driver; and
a dynamic priority selector circuit coupled to the address predecode circuit for determining which of the first and second write ports has a higher priority in response to a user input.
15. A method in a multiple port memory, the method comprising:
initiating a write operation to the multiple port memory;
decoding a first write port address to generate a first clocked predecoded write port address to access a first write port of a predetermined memory cell;
decoding a second write port address to generate a second clocked predecoded write port address to access a second write port of the predetermined memory cell, wherein the first port has a higher write priority that the second port;
providing the first clocked predecoded port address to a first word line driver comprising a first logic gate having a first input for receiving the first clocked predecoded port address, a second input for receiving a disable signal and an output to provide a first word line signal to the first write port;
providing the second clocked predecoded port address to a second word line driver comprising a second logic gate having an output coupled to the second input of the first logic gate for providing the disable signal and having an input for receiving the second clocked predecoded port address, the second word line driver coupled to provide a second word line signal to the second write port; and
using the disable signal to selectively disable access to the first write port and establish a higher priority to access the second write port than the first write port.
16. The method of claim 15 , further comprising implementing the first logic gate as a logic NAND and implementing the second logic gate as a logic NAND.
17. The method of claim 15 , further comprising implementing the first logic gate as an AND-OR-INVERT logic function and implementing the second logic gate as an AND-OR-INVERT logic function.