IP Library Granted Patent US 7,477,523
Granted Patent B2
US 7,477,523 · App. 11/678,492 · Granted Jan 13, 2009

Semiconductor device and method of manufacturing semiconductor device

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Quick Facts
Patent No.
US 7,477,523
App. No.
11/678,492
Granted
Jan 13, 2009
Kind
B2
Abstract

A semiconductor device has at least a square wiring board having a board core made of an insulating material, wires made of a metal and formed on a first surface of the board core, a solder resist film formed on the first surface to cover the wires, and openings formed by partially opening the solder resist film, wherein a plurality of the elongated wires are arranged in parallel on the bottom of the openings, a semiconductor chip having electrodes flip chip connected to the wires are arranged on the bottom of the openings of the wiring board through a conductive bonding material, and an insulating resin is provided for filling an interstice between the wiring board and the semiconductor chip, wherein the wires extend along a width direction orthogonal to a longitudinal direction of the openings, the openings comprise elongated grooves which extend along at least two opposing sides of the square of the wiring board, a pair of opposing edges of the opening along the longitudinal direction define zig-zag edges in which the widths of the opening seem to be longer and shorter in a repeating sequence, and recessed edge portions which recess toward the outside of the opening formed by the zig-zag edges in the width direction correspond to the wires, and protruded edge portions which protrude toward the inside of the opening formed by the zig-zag edges in the width direction correspond to the board core between adjoining the wires.

Claims (19)

1. A semiconductor device having at least:

a square wiring board having a board core made of an insulating material, wires made of a metal and formed on a first surface of said board core, a solder resist film formed on the first surface to cover said wires, and openings formed by partially opening said solder resist film, wherein a plurality of said wires are arranged in parallel on the bottom of said openings;

a semiconductor chip having electrodes flip chip connected to said wires arranged on the bottom of said openings of said wiring board through a conductive bonding material; and

an insulating resin for filling an interstice between said wiring board and said semiconductor chip,

wherein said wires extend along a width direction orthogonal to a longitudinal direction of said openings,

said openings comprise elongated grooves which extend along at least two opposing sides of the square of said wiring board,

a pair of opposing edges of said opening along the longitudinal direction define zig-zag edges in which the widths of the opening seem to be longer and shorter in a repeating sequence, and

recessed edge portions which recess toward the outside of said opening formed by said zig-zag edges in the width direction correspond to said wires, and protruded edge portions which protrude toward the inside of said opening formed by said zig-zag edges in the width direction correspond to said board core between adjoining said wires.

2. The semiconductor device according to claim 1 , wherein said zig-zag edge is a linearly bent edge.

3. The semiconductor device according to claim 1 , wherein said zig-zag edge is an edge undulated into a wavy shape.

4. The semiconductor device according to claim 1 , wherein said wire in said opening is formed with a plated film made of metal on a surface thereof.

5. A method of manufacturing a semiconductor device having the steps of:

(a) providing a square wiring board having a board core made of an insulating material, wires made of a metal and formed on a first surface of said board core, a solder resist film formed on the first surface to cover said wires, and a plurality of openings formed by partially opening said solder resist film, wherein a plurality of said wires are arranged in parallel on the bottom of said opening;

(b) coating an insulating resin in an area surrounded by said plurality of openings on the first surface of said wiring board; and

(c) pressing a semiconductor chip against the first surface of said wiring board in a state in which electrodes face the first surface to flip chip connect said each electrode to said wire in said openings, and opening up said insulating resin with said semiconductor chip to fill an interstice between said wiring board and said semiconductor chip,

wherein in said step (a), when said openings are formed through said solder resist film, said openings are formed as elongated grooves which extend along at least two opposing sides of said wiring board which is square in shape, and said wires are formed to extend in a width direction orthogonal to a longitudinal direction of said openings,

a pair of opposing edges of said opening along the longitudinal direction are formed in zig-zag edges in which the widths of the opening seem to be longer and shorter in a repeating sequence,

recessed edge portions which recess toward the outside of said opening formed by said zig-zag edges in the width direction are formed to correspond to said wires, and

protruded edge portions which protrude toward the inside of said opening formed by said zig-zag edges in the width direction are formed to correspond to said board core between adjoining said wires.

Assignments (9)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 9, 2014
From: ELPIDA MEMORY, INC.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 032645/0422 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 7, 2007
From: TSUJI, DAISUKE
To: ELPIDA MEMORY, INC.
Reel/Frame 019257/0847 →