METHOD OF WIRE BONDING OVER ACTIVE AREA OF A SEMICONDUCTOR CIRCUIT
A method and structure are provided to enable wire bond connections over active and/or passive devices and/or low-k dielectrics, formed on an Integrated Circuit die. A semiconductor substrate having active and/or passive devices is provided, with interconnect metallization formed over the active and/or passive devices. A passivation layer formed over the interconnect metallization is provided, wherein openings are formed in the passivation layer to an upper metal layer of the interconnect metallization. Compliant metal bond pads are formed over the passivation layer, wherein the compliant metal bond pads are connected through the openings to the upper metal layer, and wherein the compliant metal bond pads are formed substantially over the active and/or passive devices. The compliant metal bond pads may be formed of a composite metal structure.
1 . A circuit component, comprising:
a semiconductor substrate;
a dielectric layer having a dielectric constant of less than 3.0 over said semiconductor substrate;
a passivation layer over said dielectric layer;
a polymer layer over said passivation layer;
a metal pad on said polymer layer and over said dielectric layer; and
a wire bonded to said metal pad.
2 . The circuit component of claim 1 , wherein said metal pad comprises a first gold layer and a second gold layer on said first gold layer.
3 . The circuit component of claim 1 , wherein said metal pad comprises a gold layer.
4 . The circuit component of claim 1 , wherein said metal pad comprises a titanium-containing layer, and a gold layer on said titanium-containing layer.
5 . The circuit component of claim 1 , wherein said metal pad comprises a gold layer having a thickness of greater than 1 m.
6 . The circuit component of claim 1 , wherein said metal pad comprises a first copper layer and a second copper layer on said first copper layer.
7 . The circuit component of claim 1 , wherein said metal pad comprises a copper layer, a nickel layer on said copper layer, and a gold layer on said nickel layer.
8 . The circuit component of claim 1 , wherein said metal pad comprises a copper layer with a thickness of greater than 1 m.
9 . The circuit component of claim 1 , wherein said metal pad comprises a copper layer, and a gold layer over said copper layer.
10 . The circuit component of claim 1 , wherein said metal pad comprises a copper layer.
11 . The circuit component of claim 1 , wherein said polymer layer comprises polyimide.
12 . The circuit component of claim 1 , wherein said polymer layer comprises benzocyclobutene (BCB).
13 . The circuit component of claim 1 , wherein said passivation layer comprises silicon nitride.
14 . The circuit component of claim 1 , wherein said passivation layer comprises nitride.
15 . The circuit component of claim 1 , wherein said passivation layer comprises silicon oxide and silicon nitride.
16 . A circuit component, comprising:
a semiconductor substrate;
a dielectric layer having a dielectric constant of less than 3.0 over said semiconductor substrate;
a first metal pad over said dielectric layer;
a passivation layer over said dielectric layer, an opening in said passivation layer exposing said first metal pad;
a second metal pad over said dielectric layer, wherein said second metal pad is connected to said first metal pad through said opening, and wherein said second metal pad comprises a first gold layer; and
a wire bonded to said second metal pad.
17 . The circuit component of claim 16 , wherein said second metal pad further comprises a second gold layer under said first gold layer.
18 . The circuit component of claim 16 , wherein said second metal pad further comprises a titanium-containing layer under said first gold layer.
19 . The circuit component of claim 16 , wherein said first gold layer has a thickness of greater than 1 m.
20 . The circuit component of claim 16 , wherein said second metal pad further comprises a copper layer under said first gold layer.
21 . The circuit component of claim 16 , wherein said second metal pad further comprises a copper layer, and a nickel layer on said copper layer, wherein said first gold layer is on said nickel layer.
22 . The circuit component of claim 16 , wherein said second metal pad further comprises a copper layer with a thickness of greater than 1 m under said first gold layer.
23 . The circuit component of claim 16 , wherein said passivation layer comprises silicon nitride.
24 . The circuit component of claim 16 , wherein said passivation layer comprises nitride.
25 . The circuit component of claim 16 , wherein said passivation layer comprises silicon oxide and silicon nitride.
26 . The circuit component of claim 16 , wherein said second metal pad is over said first metal pad.
27 . A circuit component, comprising:
a semiconductor substrate;
a dielectric layer having a dielectric constant of less than 3.0 over said semiconductor substrate;
a passivation layer over said dielectric layer;
a metal pad over said passivation layer, wherein said metal pad comprises a first gold layer; and
a wire bonded to said metal pad.
28 . The circuit component of claim 27 , wherein said metal pad further comprises a second gold layer under said first gold layer.
29 . The circuit component of claim 27 , wherein said metal pad further comprises a titanium-containing layer under said first gold layer.
30 . The circuit component of claim 27 , wherein said first gold layer has a thickness of greater than 1 m.
31 . The circuit component of claim 27 , wherein said metal pad further comprises a copper layer under said first gold layer.
32 . The circuit component of claim 27 , wherein said metal pad further comprises a copper layer, and a nickel layer on said copper layer, wherein said first gold layer is on said nickel layer.
33 . The circuit component of claim 27 , wherein said second metal pad further comprises a copper layer with a thickness of greater than 1 m under said first gold layer.
34 . The circuit component of claim 27 , wherein said passivation layer comprises silicon nitride.
35 . The circuit component of claim 27 , wherein said passivation layer comprises a silicon oxide and a silicon nitride over said silicon oxide.