SEMICONDUCTOR DEVICE WITH HIGH CONDUCTIVITY REGION USING SHALLOW TRENCH

1 . An integrated circuit comprising:

a semiconductor substrate having an opening provided therein;

a first doped high conductivity region formed from doped material in the opening, the opening containing only the doped material, and a diffused dopant region proximate the doped material in the opening; and

a structure over the first doped high conductivity region selected from a group consisting of a wordline, a gate, a dielectric layer, and a combination thereof.

2 . The integrated circuit as claimed in claim 1 wherein the first doped high conductivity region and the diffused dopant region contain the same dopant.

3 . The integrated circuit as claimed in claim 1 wherein the first doped high conductivity region is a region selected from a group consisting of a bitline, a source junction, a drain junction, an interconnect, and a combination thereof.

4 . The integrated circuit as claimed in claim 1 wherein the first doped high conductivity region has the lateral spread of dopant reduced by 50% and more over the lateral spread of dopant of an implanted bitline.

5 . The integrated circuit as claimed in claim 1 including a second doped high conductivity region within lateral straggle shorting distance of the first doped high conductivity region.

6 . The integrated circuit as claimed in claim 1 including a second doped high conductivity region within transient enhanced diffusion shorting distance of the first doped high conductivity region.

7 . The integrated circuit as claimed in claim 1 including:

a first insulating layer over the semiconductor substrate;

a charge-trapping layer over the first insulating layer; and

a second insulating layer over the charge-trapping layer.

8 . An integrated circuit comprising:

a silicon substrate having shallow trenches provided therein;

doped high conductivity regions of doped polysilicon material in the shallow trenches, the shallow trenches containing only the doped polysilicon material, the doped polysilicon material planar with the silicon substrate and diffused dopant regions around the doped polysilicon material in the shallow trenches;

a first oxide insulating layer over the silicon substrate and the doped polysilicon material;

structures over the first oxide insulating layer, the structures selected from a group consisting of wordlines, gates, dielectric layers, and a combination thereof; and

completing the integrated circuit.

9 . The integrated circuit as claimed in claim 8 wherein:

the doped high conductivity regions and the diffused dopant regions contain the same dopant; and

including:

a threshold adjustment implantation containing a different dopant from the doped high conductivity regions and the diffused dopant regions.

10 . The integrated circuit as claimed in claim 8 wherein the doped high conductivity regions are regions selected from a group consisting of bitlines, source junctions, drain junctions, interconnects, and a combination thereof.

11 . The integrated circuit as claimed in claim 8 wherein the doped high conductivity regions have the lateral spread of dopant reduced by 50% and more over the lateral spread of dopant of implanted bitlines.

12 . The integrated circuit as claimed in claim 8 wherein the doped high conductivity regions have at least two doped high conductivity regions within lateral straggle shorting distance of each other.

13 . The integrated circuit as claimed in claim 8 wherein the doped high conductivity regions have at least two doped high conductivity regions within transient enhanced diffusion shorting distance of each other.

14 . The integrated circuit as claimed in claim 8 including:

a nitride charge-trapping layer over the first insulating layer; and

an oxide second insulating layer over the nitride charge-trapping layer.