Memory device, a non-volatile semiconductor memory device and a method of forming a memory device

1. A non-volatile semiconductor memory device comprising:

a memory cell array comprising NAND strings, wherein each NAND string comprises non-volatile memory transistors connected in series;

a source line, configured to be connected with the NAND string array via select transistors; and

a peripheral portion including conductive lines, portions of the conductive lines adjoining a surface of a semiconductor carrier.

2. The non-volatile semiconductor memory device of claim 1 , comprising wherein portions of the source line are adjoining the surface of the semiconductor carrier.

3. A non-volatile semiconductor memory device comprising:

a memory cell array comprising NAND strings, wherein each NAND string comprises non-volatile memory transistors connected in series;

a source line, configured to be connected with the NAND string array via select transistors; and

a peripheral portion including conductive lines,

wherein the conductive lines and the source line are disposed in a first conductive layer.

4. The non-volatile semiconductor memory device of claim 3 , comprising wherein portions of the source lines adjoin a surface of a semiconductor carrier.

5. The non-volatile semiconductor memory device of claim 3 , comprising wherein the peripheral portion further includes transistors, each of the transistors comprising a doped portion, and the conductive lines are configured to connect the doped portions of selected ones of the transistors.

6. The non-volatile semiconductor memory device of claim 3 , wherein the peripheral portion further comprises contact plugs made of a conductive material in contact with a top side of the conductive lines.

7. The non-volatile semiconductor memory device of claim 3 , wherein the array portion further comprises conductive array lines which are disposed in a higher conductive layer, the conductive array lines being connected with the conductive lines of the peripheral portion.

8. The non-volatile semiconductor memory device of claim 3 , comprising wherein a top diameter of the conductive lines is larger than a bottom diameter of the conductive lines and wherein a top diameter of the source lines is larger than a bottom diameter of the source lines.

9. A memory device comprising:

an array portion including memory cells; and

a peripheral portion including isolation trenches disposed in a surface region of a semiconductor carrier, the isolation trenches being filled with an insulating material, and conductive lines, wherein a top diameter of the conductive lines is larger than a bottom diameter of the conductive lines and wherein portions of the conductive lines adjoin a surface of the isolation trenches.

10. The memory device of claim 9 , wherein the peripheral portion further comprises contact plugs made of a conductive material in contact with a top side of the conductive lines.

11. A memory device comprising:

an array portion including memory cells; and

a peripheral portion including conductive lines, portions of the conductive lines adjoining a surface of a semiconductor carrier,

wherein the array portion further includes source lines connected with selected ones of the memory cells, the source lines adjoining the surface of the semiconductor carrier.

12. A memory device comprising:

an array portion including memory cells; and

a peripheral portion including conductive lines, portions of the conductive lines adjoining a surface of a semiconductor carrier,

wherein the devices comprise transistors, each of the transistors comprising a doped portion, and the conductive lines are configured to connect doped portions of selected transistors.

13. A memory device comprising:

an array portion including memory cells; and

a peripheral portion including conductive lines, portions of the conductive lines adjoining a surface of a semiconductor carrier,

wherein the peripheral portion further comprises contact plugs made of a conductive material in contact with a top side of the conductive lines.

14. A memory device comprising:

an array portion including memory cells; and

a peripheral portion including conductive lines, portions of the conductive lines adjoining a surface of a semiconductor carrier,

wherein contact plugs made of a conductive material are present in the layer of the conductive lines.

15. A memory device comprising:

an array portion including memory cells; and

a peripheral portion including conductive lines, portions of the conductive lines adjoining a surface of a semiconductor carrier,

wherein a top diameter of the conductive lines is larger than a bottom diameter of the conductive lines.

16. A memory device comprising:

an array portion including memory cells and source lines in contact with selected ones of the memory cells, the source lines adjoining a surface of a semiconductor carrier; and

a peripheral portion including conductive lines, portions of the conductive lines adjoining the surface of the semiconductor carrier.

17. The memory device of claim 16 , wherein the array portion further comprises conductive array lines which are disposed in a higher conductive layer, the conductive array lines being connected with the conductive lines of the peripheral portion.

18. The memory device of claim 16 , comprising wherein a top diameter of the conductive lines is larger than a bottom diameter of the conductive lines and wherein a top diameter of the source lines is larger than a bottom diameter of the source lines.

19. A memory card including a non-volatile semiconductor memory device comprising:

a memory cell array comprising NAND strings, wherein each NAND string comprises non-volatile memory transistors connected in series;

a source line, configured to be connected with the NAND string array via select transistors; and

a peripheral portion including conductive lines, portions of the conductive lines adjoining a surface of a semiconductor carrier.

20. An electric device comprising:

a card interface;

a card slot connected to the card interface; and

a memory card including a non-volatile semiconductor memory device comprising:

a memory cell array comprising NAND strings, wherein each NAND string comprises non-volatile memory transistors connected in series;

a source line, configured to be connected with the NAND string array via select transistors;

a peripheral portion including conductive lines, portions of the conductive lines adjoining a surface of a semiconductor carrier; and

the memory card being configured to be connected and removed from the card slot.