IP Library Assignment 036776/0905
Patent Assignment
Reel/Frame 036776/0905

Assignment of Assignor's Interest

Recorded: 2015-10-05 Pages: 6
Assignor
INFINEON TECHNOLOGIES AG
Executed: 2015-07-20
Assignee
SAMSUNG ELECTRONICS CO., LTD.
129, SAMSUNG-RO, YEONGTONG-GU, SUWON-SI, GYEONGGI-DO, 443-742, KOREA, REPUBLIC OF
Covered Properties (42)
Chip Crack Stop Design for Semiconductor Chips
Patent: 6,495,918 →
Application: 09/655,461 →
Integrated Memory Circuit and Method of Forming an Integrated Memory Circuit
Patent: 6,777,725 →
Application: 10/171,643 →
Publication: US 2003/0230783
Non-Volatile Memory Cell and Fabrication Method
Patent: 6,734,063 →
Application: 10/200,423 →
Publication: US 2004/0014280
Emulation Interface System
Patent: 7,058,855 →
Application: 10/202,372 →
Publication: US 2004/0019827
Multi-Protocol Memory Card
Patent: 7,641,121 →
Application: 10/546,938 →
Publication: US 2007/0170266
Circuit, System and Method for Encoding Data to Be Stored on a Non-Volatile Memory Array
Patent: 7,197,594 →
Application: 10/667,481 →
Publication: US 2005/0066110
Data Transmission System with Reduced Power Consumption
Patent: 7,321,628 →
Application: 10/674,859 →
Publication: US 2005/0069043
Circuit Carrier and Production Thereof
Patent: 6,991,470 →
Application: 10/912,146 →
Publication: US 2005/0064732
Apparatus for Calibrating the Relative Phase of Two Reception Signals of a Memory Chip
Patent: 7,016,259 →
Application: 10/949,793 →
Publication: US 2005/0094462
Non-Volatile Memory Cell and Fabrication Method
Patent: 40,532 →
Application: 11/034,444 →
Circuit Carrier and Production Thereof
Patent: 7,153,143 →
Application: 11/292,082 →
Publication: US 2006/0084285
Semiconductor Memory and Method for Adapting the Phase Relationship Between a Clock Signal and Strobe Signal During the Acceptance of Write Data to Be Transmitted
Patent: 7,457,174 →
Application: 11/410,320 →
Publication: US 2006/0262613
Charge-Trapping Memory Device and Methods for Its Manufacturing and Operation
Patent: 7,349,254 →
Application: 11/444,289 →
Publication: US 2007/0280002
Memory Module, Memory Extension Memory Module, Memory Module System, and Method for Manufacturing a Memory Module
Patent: 7,351,072 →
Application: 11/481,676 →
Publication: US 2007/0015381
Memory Device and Method for Verifying Information Stored in Memory Cells
Patent: 7,457,144 →
Application: 11/489,702 →
Publication: US 2008/0019187
Memories, Method of Storing Data in a Memory and Method of Determining Memory Cell Sector Quality
Patent: 7,707,380 →
Application: 11/541,392 →
Publication: US 2008/0082776
Memory Cell
Patent: 7,554,856 →
Application: 11/544,287 →
Publication: US 2008/0084757
Control Signal Training
Patent: 7,411,862 →
Application: 11/560,293 →
Publication: US 2008/0112235
Memory Device
Patent: 7,875,985 →
Application: 11/644,044 →
Publication: US 2008/0150111
Memory Device with Adaptive Sense Unit and Method of Reading a Cell Array
Patent: 7,489,563 →
Application: 11/668,753 →
Publication: US 2008/0181012
Memory Device, a Non-Volatile Semiconductor Memory Device and a Method of Forming a Memory Device
Patent: 7,733,698 →
Application: 11/688,949 →
Publication: US 2008/0232170
Integrated Circuits and Methods of Manufacturing Thereof
Patent: 7,714,377 →
Application: 11/737,617 →
Publication: US 2008/0259687
Integrated Circuits; Methods for Manufacturing an Integrated Circuit; Memory Modules; Computing Systems
Patent: 7,649,779 →
Application: 11/749,028 →
Publication: US 2008/0285344
Method of Simple Chip Select for Memory Subsystems
Patent: 7,710,754 →
Application: 11/843,558 →
Publication: US 2009/0052267
Training Connections in a Memory Arrangement
Patent: 7,908,232 →
Application: 11/844,791 →
Publication: US 2008/0052256
Method of Operating an Integrated Circuit for Reading the Logical State of a Memory Cell
Patent: 7,602,649 →
Application: 11/849,828 →
Publication: US 2009/0059673
Integrated Circuit Including a First Gate Stack and a Second Gate Stack and a Method of Manufacturing
Patent: 7,875,516 →
Application: 11/855,695 →
Publication: US 2009/0072274
Integrated Circuit Having Nand Memory Cell Strings
Patent: 7,778,073 →
Application: 11/872,655 →
Publication: US 2009/0097317
Integrated Circuit Having a Memory Cell Arrangement and Method for Reading a Memory Cell State Using a Plurality of Partial Readings
Patent: 7,800,943 →
Application: 12/016,750 →
Publication: US 2009/0185425
Integrated Circuit and Method to Operate an Integrated Circuit
Patent: 7,813,169 →
Application: 12/016,774 →
Publication: US 2009/0185441
Method of Operating an Integrated Circuit, Integrated Circuit and Method to Determine an Operating Point
Patent: 7,808,833 →
Application: 12/020,977 →
Publication: US 2009/0190408
Charge-Trapping Memory Device and Methods for Its Manufacturing and Operation
Patent: 7,583,532 →
Application: 12/035,837 →
Publication: US 2008/0279004
Interface for Nand-Type Flash Memory
Patent: 8,243,516 →
Application: 12/052,414 →
Publication: US 2009/0238001
Integrated Circuit and Method for Reading the Content of a Memory Cell
Patent: 7,826,280 →
Application: 12/057,746 →
Publication: US 2009/0244992
Memory Device and Method Providing Logic Connections for Data Transfer
Patent: 7,940,575 →
Application: 12/058,191 →
Publication: US 2009/0244949
Memory Read-Out
Patent: 8,533,563 →
Application: 12/059,796 →
Publication: US 2009/0244973
Method for Forming Trenches on a Surface of a Semiconductor Substrate
Patent: 7,785,953 →
Application: 12/112,379 →
Publication: US 2009/0273017
Integrated Circuits Having a Contact Region and Methods for Manufacturing the Same
Patent: 7,915,667 →
Application: 12/137,388 →
Publication: US 2009/0309152
Integrated Circuits and Methods for Operating the Same Using a Plurality of Buffer Circuits in an Access Operation
Patent: 7,920,430 →
Application: 12/166,112 →
Publication: US 2010/0002503
Integrated Circuit with an Active Area Line Having at Least One Form-Supporting Element and Corresponding Method of Making an Integrated Circuit
Patent: 7,868,415 →
Application: 12/177,930 →
Publication: US 2010/0019345
Integrated Circuits Having a Controller to Control a Read Operation and Methods for Operating the Same
Patent: 7,864,579 →
Application: 12/178,912 →
Publication: US 2010/0020610
Memory Read-Out
Patent: 8,589,765 →
Application: 13/941,372 →
Publication: US 2013/0305124
Related Assignments (9)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest Nov 24, 2009
From: QIMONDA FLASH GMBH
To: QIMONDA AG
Reel/Frame 023561/0427 →
Assignment of Assignor's Interest Jan 12, 2010
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 023768/0001 →
Assignment of Assignor's Interest Jan 13, 2010
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 023773/0457 →
Assignment of Assignor's Interest Jan 13, 2010
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 023828/0001 →
Assignment of Assignor's Interest Jan 14, 2010
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 023853/0401 →
Assignment of Assignor's Interest Jan 14, 2010
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 023806/0001 →
Assignment of Assignor's Interest Jan 15, 2010
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 023853/0001 →
Assignment of Assignor's Interest May 8, 2015
From: QIMONDA AG
To: INFINEON TECHNOLOGIES AG
Reel/Frame 035623/0001 →
License Jun 23, 2023
From: SAMSUNG ELECTRONICS CO., LTD.
To: INTELLECTUAL KEYSTONE TECHNOLOGY LLC
Reel/Frame 064444/0863 →