Charge-trapping memory device and methods for its manufacturing and operation

1. A method for leveling bit errors in a charge-trapping memory device with a first and a second sector of memory cells, the method comprising:

validating the first sector by counting a number of bit failures occurring in memory cells of the first sector, the bit failures being caused by accessing memory cells of the second sector; and

backing up data stored in the first sector if the validating indicates a likelihood of a forthcoming failure in the first sector.

2. The method according to claim 1 , wherein:

validating the first sector comprises counting a number of tolerable bit failures and counting a number of critical bit failures; and

backing up data is performed if the number of critical bit failures exceeds a predefined threshold.

3. The method according to claim 2 , wherein backing up data is performed if any critical bit failure is present.

4. The method according to claim 2 , wherein:

the first and second sectors are subdivided into segments;

a first number of failing bits within a segment corresponds to a tolerable bit failure;

a second number of failing bits within a segment corresponds to a critical bit failure; and

a third number of failing bits within a segment corresponds to a non-correctable bit failure.

5. The method according to claim 4 , wherein the first number is one, the second number is two and the third number is three.

6. The method according to claim 1 , wherein backing up data comprises:

copying the data stored in the first sector to the second sector; and

redirecting erase, program and read operations from the first sector to the second sector.

7. The method according to claim 1 , wherein backing up data comprises:

copying the data stored in the first sector to a buffer memory;

erasing the content of the first sector; and

copying back the data stored in the buffer memory to the erased first sector.

8. A memory card device, comprising:

a charge-trapping memory device comprising:

at least two sectors, each sector comprising a data area and redundancy area, each area comprising a plurality of non-volatile memory cells, each memory cell including a charge-trapping layer;

a bit failure detector operationally connected to a first sector and adapted to detect a number of bit failures of the data area of the first sector based on data stored in the corresponding redundancy area, the bit failures being caused by accessing memory cells of a second sector; and

a controller operationally connected to the first sector and the bit failure detector and adapted to copy data stored in the data area of the first sector to another storage location if the number of bit failures is greater than a predefined threshold;

an interface for connecting the memory card to a host system; and

an interface controller connecting the interface with the charge-trapping memory device and providing the host system with access to data stored therein.

9. The memory card device according to claim 8 , wherein the controller is adapted to recycle the memory cells of the first sector by erasing or programming the memory cells to a predefined threshold level.

10. The memory card device according to claim 9 , wherein the controller is adapted to copy the data to a volatile buffer memory, recycle the memory cells of the first sector and copy back the data from the volatile buffer memory to the first sector.