Integrated circuit and method for reading the content of a memory cell

1. An integrated circuit comprising:

at least one memory cell;

a read circuit configured to read the memory cell, wherein the read circuit comprises an output holding circuit configured to hold a memory cell content signal read from the memory cell;

an enable circuit configured to provide the memory cell content signal at an output of the read circuit only when the memory cell fulfills a predefined criterion,

wherein the enable circuit further comprises an output holding circuit clock signal generator circuit configured to provide an output holding circuit clock signal;

a valid bit memory cell storing information as to whether the memory cell is a valid bit memory cell;

a valid bit memory cell sense amplifier circuit;

wherein an input of the valid bit memory cell sense amplifier circuit is coupled with the valid bit memory cell to receive a valid bit memory cell content signal;

wherein an enable input of the valid bit memory cell sense amplifier circuit is configured to receive a valid bit memory cell sense amplifier circuit enable signal;

wherein an output of the valid bit memory cell sense amplifier circuit is coupled with the enable input of a memory cell sense amplifier circuit of the read circuit.

2. The integrated circuit of claim 1 , further comprising:

a valid bit memory cell signal holding circuit;

wherein a data input of the valid bit memory cell signal holding circuit is coupled with the output of the valid bit memory cell sense amplifier circuit;

wherein an output of the valid bit memory cell signal holding circuit is coupled with the enable input of the memory cell sense amplifier circuit.

3. The integrated circuit of claim 2 , wherein a clock input of the valid bit memory cell signal holding circuit is configured to receive a memory cell holding circuit clock signal.

4. The integrated circuit of claim 3 , further comprising:

an output holding circuit clock signal generator circuit coupled with the clock input of the valid bit memory cell signal holding circuit to provide the memory cell holding circuit clock signal.

5. The integrated circuit of claim 4 , wherein the enable circuit further comprises a delay circuit configured to delay the output holding circuit clock signal compared with the memory cell holding circuit clock signal.

6. A method for reading a memory cell, the method comprising:

reading the memory cell, thereby providing a memory cell content signal;

determining whether the memo cell fulfills a predetermined criterion; and

providing the memory cell content signal at an output of a read circuit of the memory cell arrangement only if the memory cell fulfills the predefined criterion,

wherein providing the memory cell content signal at the output of the read circuit comprises providing the memory cell content signal at an output of an output holding circuit configured to hold a memory cell content signal read from the memory cell of the memory cell arrangement only in case the memory cell fulfills the predefined criterion,

wherein the read circuit comprises a memory cell sense amplifier circuit;

wherein the memory cell content signal is supplied to an input of the memory cell sense amplifier circuit;

wherein a memory cell sense amplifier circuit enable signal is supplied to an enable input of the memory cell sense amplifier circuit; and

wherein an output signal of the memory cell sense amplifier circuit is supplied to the output holding circuit,

wherein the determining whether the memory cell fulfills a predetermined criterion comprises determining whether the memory cell is a valid bit memory cell;

wherein the read information as to whether the memory cell is a valid bit memory cell is supplied to a valid bit memory cell sense amplifier circuit;

wherein an output signal of the valid bit memory cell sense amplifier circuit is supplied to a valid bit memory cell signal holding circuit;

wherein an output signal of the valid bit memory cell signal holding circuit is supplied to the enable input of the memory cell sense amplifier circuit;

wherein a memory cell holding circuit clock signal is supplied to the clock input of the valid bit memory cell signal holding circuit; and

wherein the output holding circuit clock signal is delayed compared with the memory cell holding circuit clock signal.