Method of making three dimensional NAND memory

1. A method of making a monolithic, three dimensional NAND string, comprising:

forming a first memory cell over a second memory cell;

forming a first word line for the first memory cell;

forming a second word line for the second memory cell;

forming a bit line; and

forming a source line;

wherein:

the first word line extends from the first memory cell in a first direction;

the second word line extends from the second memory cell in a second direction not parallel to the first direction;

the NAND string is formed vertically over a substrate;

a select transistor is located on the substrate or in a trench in the substrate;

the first memory cell is located in a first device level;

the second memory cell is located in a second device level located on the select transistor and below the first device level;

a semiconductor active region of the first memory cell is formed epitaxially on a semiconductor active region of the second memory cell;

the semiconductor active region of the second memory cell is formed epitaxially on a semiconductor active region of the select transistor;

a first charge storage dielectric is located between the semiconductor active region of the first memory cell and the first word line;

a second charge storage dielectric is located between the semiconductor active region of the second memory cell and the second word line;

the semiconductor active region of the first memory cell comprises a first pillar;

the semiconductor active region of the second memory cell comprises a second pillar;

the semiconductor active region of the select transistor comprises a third pillar;

the first pillar and the second pillar each comprise an upper second conductivity type semiconductor region above a first conductivity type semiconductor region above a lower second conductivity type region;

the lower second conductivity type semiconductor region in the first pillar contacts the upper second conductivity type semiconductor region in the second pillar;

the first pillar is not aligned with the second pillar, such that the first pillar extends laterally past the second pillar;

the second pillar is not aligned with the third pillar, such that the second pillar extends laterally past the third pillar;

the first, second, and third pillars are disposed about a first, second, and third central axis, respectively, each of which extend in a vertical direction substantially normal to the substrate;

the first central axis is laterally offset from the second central axis; and

the second central axis is laterally offset from the third central axis.

2. The method of claim 1 , wherein the first direction is perpendicular to the second direction.

3. The method of claim 1 , wherein the second direction is oriented at an angle of 1 to 90 degrees with respect to the first direction.

4. The method of claim 1 , wherein:

the first word line extends in the first direction from the first memory cell to a memory cell of a first separate NAND string which does not comprise the first memory cell; and

the second word line extends in the second direction from the second memory cell to a memory cell of a second separate NAND string which does not comprise the second memory cell.

5. The method of claim 1 , wherein the select transistor is located in the trench in the substrate.

6. The method of claim 5 , wherein the trench is an elongated trench having a longitudinal dimension extending substantially linearly along the substrate.

7. The method of claim 6 , wherein a width of the trench along a lateral dimension is narrower relative to a length of the trench along the longitudinal dimension.

8. The method of claim 1 , wherein the select transistor is located on the substrate.