Integrated MPE-FEC RAM for DVB-H receivers
A MPE-FEC memory chip and method for use in a DVB-H receiver, wherein the memory chip comprises a TS demux; a RS decoder; a system bus; and a RAM unit adapted to simultaneously interface to the TS demux, the RS decoder, and the system bus through time-multiplexing, wherein the RAM unit is adapted to (i) access multiple-words per clock cycle, and (ii) cache write and read accesses to reduce memory access from the TS demux and the system bus, and wherein the RAM unit is adapted to be clocked at a speed higher than an interfacing data-path to increase an effective throughput of the RAM unit. The RAM unit may comprise multiple RAM sub units, wherein while a first RAM sub unit is clock gated, the remaining multiple RAM sub units are accessible.
1. A Multi-Protocol Encapsulator Forward Error Connection (MPE-FEC) memory chip for use in a Digital Video Broadcasting over Handheld (DVB-H) receiver, said memory chip comprising:
a Transport-stream packet de-multiplexer (TS demux);
a Reed-Solomon (RS) decoder;
a system bus; and
a random access memory (RAM) unit that simultaneously interfaces to said TS demux, said RS decoder, and said system bus through time-multiplexing,
wherein said RAM unit (i) accesses multiple-words per clock cycle, and (ii) caches write and read accesses to reduce memory access from said TS demux and said system bus, and
wherein said RAM unit clocks at a speed higher than an interfacing data-path to increase an effective throughput of said RAM unit.
2. The memory chip of claim 1 , wherein said RAM unit comprises multiple RAM sub units, wherein while a first RAM sub unit is clock gated, the remaining multiple RAM sub units are accessible.
3. The memory chip of claim 1 , further comprising a register cache that is external to said RAM unit, wherein said register cache is adapted to decrease a frequency of read and write processes occurring with respect to said RAM unit.
4. The memory chip of claim 1 , wherein said RAM unit is a single port RAM unit that is adapted to be clocked at approximately twice a system clock rate.
5. The memory chip of claim 4 , wherein a first virtual port of said single port RAM unit is shared by a RS decoder read and write access.
6. The memory chip of claim 4 , wherein a second virtual port of said single port RAM unit is shared by a post-processing system output read, control logic access, and a TS demux write access.
7. The memory chip of claim 1 , wherein an amount of memory of said RAM unit is adapted to be extended by a fractional amount of a complete video frame.
8. The memory chip of claim 7 , wherein the amount of extended fractional-frame memory is adapted to store a beginning portion of a second incoming video frame during which said RS decoder can complete a FEC process on a first video frame.
9. The memory chip of claim 8 , wherein a remaining portion of said second incoming video frame overwrites a region wherein said first video frame was stored after said first video frame begins to be read out.
10. The memory chip of claim 1 , further comprising a demodulator positioned on a same silicon chip as said RAM unit, said TS demux said RS decoder, and said system bus.
11. A Multi-Protocol Encapsulator Forward Error Connection (MPE-FEC) memory chip for use in a Digital Video Broadcasting over Handheld (DVB-H) receiver, said memory chip comprising:
a Transport-stream packet de-multiplexer (TS demux);
a Reed-Solomon (RS) decoder;
a system bus;
a random access memory (RAM) unit that simultaneously interfaces to said TS demux, said RS decoder, and said system bus through time-multiplexing; and
a demodulator positioned on a same silicon chip as said RAM unit, said TS demux said RS decoder, and said system bus,
wherein said RAM unit (i) accesses multiple-words per clock cycle, and (ii) caches write and read accesses to reduce memory access from said TS demux and said system bus, and
wherein said RAM unit clocks at a speed higher than an interfacing data-path to increase an effective throughput of said RAM unit.
12. A method of processing video internet protocol (IP) datagrams in a Digital Video Broadcasting over Handheld (DVB-H) receiver, wherein said DVB-H receiver comprises a Multi-Protocol Encapsulator Forward Error Connection (MPE-FEC) memory chip comprising a Transport-stream (TS) packet de-multiplexer (TS demux); a Reed-Solomon (RS) decoder; a system bus; and a random access memory (RAM) unit that simultaneously interfaces to said TS demux, said RS decoder, and said system bus through time-multiplexing, said method comprising:
configuring said RAM unit to access multiple-words per cycle and cache read and write accesses to said RAM unit to reduce memory access from said TS demux and said system bus; and
clocking said RAM unit at a speed higher than an interfacing data-path to increase an effective throughput of said RAM unit.
13. The method of claim 12 , further comprising splitting said RAM unit into multiple smaller RAM subunits.
14. The method of claim 12 , further comprising using a register cache that is external to said RAM unit to decrease a frequency of read and write processes occurring with respect to said RAM unit.
15. The method of claim 12 , further comprising clocking said RAM unit at approximately twice a system clock rate.
16. The method of claim 12 , wherein an amount of memory of said RAM unit is adapted to be extended by a fractional amount of a complete video frame.
17. The method of claim 16 , wherein the amount of extended fractional-frame memory is adapted to store a beginning portion of a second incoming video frame during which said RS decoder can complete a FEC process on a first video frame.
18. The method of claim 17 , wherein a remaining portion of said second incoming video frame overwrites a region wherein said first video frame was stored after said first video frame begins to be read out.
19. The method of claim 12 , further comprising positioning a demodulator on a same silicon chip as said RAM unit, said TS demux said RS decoder, and said system bus.
20. The method of claim 12 , further comprising using a circular addressing scheme to allow the chip to receive back-to-back data bursts without doubling a size of said RAM unit.