NAND flash memory with fixed charge
A string of nonvolatile memory cells connected in series includes fixed charges located between floating gates and the underlying substrate surface. Such a fixed charge affects distribution of charge carriers in an underlying portion of the substrate and thus affects threshold voltage of a device. A fixed charge layer may extend over source/drain regions also.
1. A NAND flash memory array comprising:
a plurality of floating gate memory cells connected in series by conductive source/drain regions in a substrate having a surface, an individual floating gate memory cell including a floating gate and a spatially fixed charge layer portion, the fixed charge layer portion located between the floating gate and an underlying gate dielectric layer portion, the gate dielectric layer portion overlying the substrate surface, the spatially fixed charge layer portion induces an inversion layer in the substrate below the gate dielectric layer portion.
2. The NAND flash memory array of claim 1 wherein an individual source/drain region underlies an additional fixed charge layer portion, the additional fixed charge layer portion separated from the source/drain region by an additional dielectric layer portion.
3. The NAND flash memory array of claim 2 wherein the fixed charge layer portion and the additional fixed charge layer portion are different portions of a common fixed charge layer.
4. The NAND flash memory array of claim 2 wherein the fixed charge layer portion and the additional fixed charge layer portion have different amounts of charge per unit area.
5. The NAND flash memory array of claim 2 wherein the fixed charge layer portion is formed from a first fixed charge layer and the additional fixed charge layer portion is formed from a second fixed charge layer.
6. The NAND flash memory array of claim 1 further comprising a plurality of control gates, an individual control gate overlying the floating gate.
7. The NAND flash memory array of claim 1 further comprising a plurality of control gates, a first control gate extending between the floating gate and a first neighboring floating gate on a first side and a second control gate extending between the floating gate and a second neighboring floating gate on a second side.
8. The NAND flash memory array of claim 1 further comprising a select gate at an end of the plurality of floating gate memory cells, the select gate separated from the substrate surface by a fixed charge layer portion.
9. A NAND flash memory array comprising:
a substrate;
a plurality of floating gates overlying the substrate;
a plurality of control gates extending between floating gates such that each of the plurality of floating gates couples to two of the plurality of control gates;
a plurality of source/drain regions in areas of the substrate under control gates; and
a spatially fixed charge layer that extends between the substrate and the plurality of floating gates and also extends between the substrate and the plurality of control gates, the fixed charge layer separated from the substrate by a gate dielectric layer, the spatially fixed charge layer creates inversion layers in the substrate underlying the plurality of floating gates.
10. The NAND flash memory array of claim 9 wherein the fixed charge layer is comprised of nitrided Silicon Dioxide.
11. The NAND flash memory array of claim 9 wherein the fixed charge layer is comprised of a dielectric layer implanted with ions.
12. The NAND flash memory array of claim 9 wherein the source/drain regions are formed by charge carriers attracted to the fixed charge layer, without source/drain implants.
13. The NAND flash memory array of claim 1 wherein the fixed charge layer affects band bending in the substrate below the gate dielectric layer portion to a sufficient extent to cause the inversion layer to extend between two of the conductive source/drain regions.
14. The NAND flash memory array of claim 1 wherein the charge per unit area of the fixed charge layer is sufficiently high to cause the inversion layer to extend between two of the conductive source/drain regions, the inversion layer has a first type of conductivity, the substrate has a second type of conductivity in a region other than the inversion layer, the first type of conductivity is opposite the second type of conductivity.
15. The NAND flash memory array of claim 1 wherein the charge per unit area of the fixed charge layer is sufficiently high to cause the floating gate memory cells to operate in depletion mode due to the inversion layer.
16. The NAND flash memory array of claim 1 wherein charges in the fixed charge layer remain fixed in place.