Modifying integrated circuit designs to achieve multiple operating frequency targets
A first integrated circuit design with a first maximum operating frequency is modified to achieve a second integrated circuit design with a second maximum operating frequency. The integrated circuit design comprises an arrangement of cells. Each of these cells drives a signal that propagates through a net of other circuit elements to one or more nodes that are limited by respective signal timing constraints. An analytical cost function is assigned to each of the cells. Each analytical cost function comprises a value for its respective cell that is based on one or more speed-related factors indicative of the impact of the respective cell on the first maximum operating frequency of the first integrated circuit design. One or more of the cells are replaced with different cells based on the determined analytical cost functions.
1. A method of modifying a first integrated circuit design with a first maximum operating frequency to achieve a second integrated circuit design with a second maximum operating frequency, the first integrated circuit design comprising an arrangement of a plurality of cells, each of the plurality of cells driving a respective signal through a net of other circuit elements to one or more nodes limited by respective signal timing constraints, the method comprising the steps of:
assigning analytical cost functions to respective ones of the plurality of cells, each analytical cost function comprising a value for its respective cell that is based on one or more speed-related factors indicative of the impact of the respective cell on the first maximum operating frequency of the first integrated circuit design; and
replacing one or more of the plurality of cells with different cells based on the determined analytical cost functions;
each of the first and second integrated circuit designs comprising a physical layout of its corresponding cells;
at least a given one of the analytical cost functions comprising a value that is based on a weighted combination of at least two speed-related factors using respective unequal weights, said at least two speed-related factors including at least one factor other than propagation delay, signal transition time and capacitive load, said at least one factor comprising signal delay due to crosstalk on the net of other circuit elements driven by the respective cell;
wherein the assigning and replacing steps are applied to the physical layout of the first integrated circuit design and are implemented in a data processing system comprising a memory and a data processor coupled to the memory;
the method further comprising the step of transforming the second integrated circuit design into integrated circuit hardware.
2. The method of claim 1 , wherein the one or more speed-related factors comprise at least one of the following:
number of nodes not meeting their respective signal timing constraints that are driven by the respective cell; and
distribution of times by which nodes not meeting their respective timing constraints that are driven by the respective cell miss their respective signal timing constraints.
3. The method of claim 1 , wherein each analytical cost function comprises a value that is based on a linear combination of at least two speed-related factors.
4. The method of claim 3 , wherein the at least two speed-related factors are weighted relative to one another when determining the analytical cost functions.
5. The method of claim 1 , wherein the one or more speed-related factors are determined by static timing analysis.
6. The method of claim 1 , wherein a cell that is replaced in the replacing step is replaced by a different cell with the same areal dimensions as the cell being replaced.
7. The method of claim 1 , wherein a cell that is replaced in the replacing step is replaced by a different cell with the same configuration of inputs and outputs as the cell being replaced.
8. The method of claim 1 , wherein a cell that is replaced in the replacing step is replaced by a different cell with a different set of threshold voltages from the cell being replaced.
9. The method of claim 1 , wherein at least one of the one or more nodes driven by each of the plurality of cells and limited by respective signal timing constraints comprises an input or an output of a sequential logic element.
10. The method of claim 9 , wherein the signal timing constraint on the at least one of the one or more nodes is determined by at least one of a setup time and a hold time of the sequential logic element.
11. The method of claim 1 wherein the analytical cost function is non-linear in one or more of the speed-related factors.
12. An article of manufacture comprising a machine-readable storage medium storing one or more programs for use in modifying a first integrated circuit design with a first maximum operating frequency to achieve a second integrated circuit design with a second maximum operating frequency, the first integrated circuit design comprising an arrangement of a plurality of cells, each of the plurality of cells driving a respective signal through a net of other circuit elements to one or more nodes limited by respective signal timing constraints, the one or more programs operative to cause a data processing system comprising a memory and a data processor coupled to the memory to execute at least the steps of:
assigning analytical cost functions to respective ones of the plurality of cells, each analytical cost function comprising a value for its respective cell that is based on one or more speed-related factors indicative of the impact of the respective cell on the first maximum operating frequency of the first integrated circuit design; and
replacing one or more of the plurality of cells with different cells based on the determined analytical cost functions;
each of the first and second integrated circuit designs comprising a physical layout of its corresponding cells;
wherein the assigning and replacing steps are applied to the physical layout of the first integrated circuit design;
at least a given one of the analytical cost functions comprising a value that is based on a weighted combination of at least two speed-related factors using respective unequal weights, said at least two speed-related factors including at least one factor other than propagation delay, signal transition time and capacitive load, said at least one factor comprising signal delay due to crosstalk on the net of other circuit elements driven by the respective cell.
13. A data processing system comprising a memory and a data processor coupled to the memory for modifying a first integrated circuit design with a first maximum operating frequency to achieve a second integrated circuit design with a second maximum operating frequency, the first integrated circuit design comprising an arrangement of a plurality of cells, each of the plurality of cells driving a respective signal through a net of other circuit elements to one or more nodes limited by respective signal timing constraints, the data processing system operative to perform the steps of:
assigning analytical cost functions to respective ones of the plurality of cells, each analytical cost function comprising a value for its respective cell that is based on one or more speed-related factors indicative of the impact of the respective cell on the first maximum operating frequency of the first integrated circuit design; and
replacing one or more of the plurality of cells with different cells based on the determined analytical cost functions;
each of the first and second integrated circuit designs comprising a physical layout of its corresponding cells;
wherein the assigning and replacing steps are applied to the physical layout of the first integrated circuit design;
at least a given one of the analytical cost functions comprising a value that is based on a weighted combination of at least two speed-related factors using respective unequal weights, said at least two speed-related factors including at least one factor other than propagation delay, signal transition time and capacitive load, said at least one factor comprising signal delay due to crosstalk on the net of other circuit elements driven by the respective cell.
14. The data processing system of claim 13 , wherein the one or more speed-related factors comprise at least one of the following:
number of nodes not meeting their respective signal timing constraints that are driven by the respective cell; and
distribution of times by which nodes not meeting their respective timing constraints that are driven by the respective cell miss their respective signal timing constraints.
15. The data processing system of claim 13 , wherein the one or more speed-related factors are determined by static timing analysis.
16. The data processing system of claim 13 , wherein the data processing system is further operative to perform the step of determining the power consumption of the integrated circuit during operation.
17. The data processing system of claim 13 , wherein each analytical cost function comprises a value that is based on a linear combination of at least two speed-related factors.
18. The data processing system of claim 17 , wherein the at least two speed-related factors are weighted relative to one another when determining the analytical cost functions.
19. The data processing system of claim 13 , wherein a cell that is replaced in the replacing step is replaced by a different cell with the same areal dimensions as the cell being replaced.
20. The data processing system of claim 13 , wherein a cell that is replaced in the replacing step is replaced by a different cell with the same configuration of inputs and outputs as the cell being replaced.
21. The data processing system of claim 13 , wherein a cell that is replaced in the replacing step is replaced by a different cell with a different set of threshold voltages from the cell being replaced.