MEMORY SYSTEM WITH DEPLETION GATE

1 . A memory system comprising:

providing a substrate;

forming a first insulator layer over the substrate;

forming a charge-storage layer over the first insulator layer;

forming a second insulator layer over the charge-storage layer; and

forming a depletion gate having a depletion phenomenon over the second insulator layer.

2 . The system as claimed in claim 1 wherein forming the depletion gate includes applying a dopant on a gate to provide the depletion phenomenon.

3 . The system as claimed in claim 1 wherein forming the charge-storage layer includes forming a nitride layer for storing a charge.

4 . The system as claimed in claim 1 wherein forming the first insulator layer includes forming an oxide layer for insulating the charge-storage layer.

5 . The system as claimed in claim 1 further comprising forming an electronics system including the memory system.

6 . A memory system comprising:

providing a semiconductor substrate having a first region and a second region;

forming a first insulator layer over the first region and the second region of the semiconductor substrate;

forming a charge-storage layer as a nitride layer over the first insulator layer;

forming a second insulator layer as an oxide on the charge-storage layer; and

forming a depletion gate having a dopant for a depletion phenomenon over the second insulator layer.

7 . The system as claimed in claim 6 wherein forming the depletion gate includes applying an N+ dopant on a gate to provide the depletion phenomenon.

8 . The system as claimed in claim 6 wherein forming the charge-storage layer includes forming a silicon rich nitride layer for storing a charge.

9 . The system as claimed in claim 6 wherein forming the first insulator layer includes forming a silicon dioxide layer for insulating the charge-storage layer.

10 . The system as claimed in claim 6 wherein forming the second insulator layer includes forming a silicon dioxide layer for insulating the charge storage-layer.

11 . A memory system comprising:

a substrate;

a first insulator layer over the substrate;

a charge-storage layer over the first insulator layer;

a second insulator layer over the charge-storage layer; and

a depletion gate having a depletion phenomenon over the second insulator layer.

12 . The system as claimed in claim 11 wherein the depletion gate includes a dopant on a gate to provide the depletion phenomenon.

13 . The system as claimed in claim 11 wherein the charge-storage layer is a nitride layer for storing a charge.

14 . The system as claimed in claim 11 wherein the first insulator layer is an oxide layer for insulating the charge-storage layer.

15 . The system as claimed in claim 11 further comprising an electronics system including the memory system.

16 . The system as claimed in claim 11 wherein:

the substrate is a semiconductor substrate having a first region and a second region;

the first insulator layer is over the first region and the second region of the semiconductor substrate;

the charge-storage layer is a nitride layer;

the second insulator layer is an oxide on the charge-storage layer; and

the depletion gate is a depletion gate having a dopant.

17 . The system as claimed in claim 16 wherein the depletion gate includes an N+ dopant on a gate to provide the depletion phenomenon.

18 . The system as claimed in claim 16 wherein the charge-storage layer includes a silicon rich nitride layer for storing a charge.

19 . The system as claimed in claim 16 wherein the first insulator layer is a silicon dioxide layer for insulating the charge-storage layer.

20 . The system as claimed in claim 16 wherein the second insulator layer is a silicon dioxide layer for insulating the charge storage-layer.