Nano-enabled memory devices and anisotropic charge carrying arrays
Methods and apparatuses for nanoenabled memory devices and anisotropic charge carrying arrays are described. In an aspect, a memory device includes a substrate, a source region of the substrate, and a drain region of the substrate. A population of nanoelements is deposited on the substrate above a channel region, the population of nanolements in one embodiment including metal quantum dots. A tunnel dielectric layer is formed on the substrate overlying the channel region, and a metal migration barrier layer is deposited over the dielectric layer. A gate contact is formed over the thin film of nanoelements. The nanoelements allow for reduced lateral charge transfer. The memory device may be a single or multistate memory device. In a multistate memory device which comprises one or more quantum dots or molecules having a plurality of discrete energy levels, a method is disclosed for charging and/or discharging the device which comprises filling each of the plurality of discrete energy levels of each dot or molecule with one or more electrons, and subsequently removing individual electrons at a time from each discrete energy level of the one or more dots or molecules.
1. A memory device, comprising:
a substrate;
a source region of said substrate;
a drain region of said substrate;
a channel region between said source and drain regions;
a charge storage region above said channel region including a population of nanoelements which are deposited in said charge storage region after they are grown, said nanoelements comprising a core made from ruthenium or iridium and a shell layer that surrounds said core which shell layer is an oxidized layer of each of said nanoelement;
a dielectric layer deposited between said substrate and said charge storage region; and
a gate contact formed above or below said population of nanoelements.
2. The memory device of claim 1 , wherein the nanoelements comprise substantially spherical nanoelements or quantum dots.
3. The memory device of claim 1 , wherein the nanoelements comprise ruthenium.
4. The memory device of claim 1 , further comprising a nitride layer deposited or formed on said dielectric layer adjacent to said charge storage region.
5. The memory device of claim 4 , wherein the nitride layer comprises silicon nitride.