Self-aligned silicon carbide semiconductor devices and methods of making the same
View Patent ↗A self-aligned silicon carbide power MESFET with improved current stability and a method of making the device are described. The device, which includes raised source and drain regions separated by a gate recess, has improved current stability as a result of reduced surface trapping effects even at low gate biases. The device can be made using a self-aligned process in which a substrate comprising an n + -doped SiC layer on an n-doped SiC channel layer is etched to define raised source and drain regions (e.g., raised fingers) using a metal etch mask. The metal etch mask is then annealed to form source and drain ohmic contacts. A single- or multilayer dielectric film is then grown or deposited and anisotropically etched. A Schottky contact layer and a final metal layer are subsequently deposited using evaporation or another anisotropic deposition technique followed by an optional isotropic etch of dielectric layer or layers.
1. A method of making a semiconductor device comprising:
selectively etching a first layer of n-type SiC on a second layer of n-type SiC using a metal etch mask on the first layer of n-type SiC, wherein the second layer of n-type SiC is less heavily doped with an n-type dopant than the first layer of n-type SiC, wherein the second layer of n-type SiC is on a layer of p-type SiC which is on a SiC substrate layer, and wherein etching comprises etching through the first layer of n-type SiC and into the second layer of n-type SiC to form a plurality of discrete raised regions each having an upper surface, the plurality of discrete raised regions being spaced from one another thereby defining one or more recesses between adjacent raised regions, the one or more recesses having a bottom surface and sidewalls;
annealing the metal etch mask on the first layer of n-type SiC to form ohmic contacts on upper surfaces of the raised regions;
subsequently depositing one or more layers of dielectric material on exposed surfaces of the first and second layers of n-type SiC including the bottom surface and sidewalls of the one or more recesses;
anisotropically etching through the one or more dielectric layers on the bottom of the one or more recesses to expose second layer of n-type SiC; and
depositing a Schottky metal on the exposed second layer of n-type SiC in the one or more recesses to form a gate junction.
2. The method of claim 1 , wherein the metal etch mask comprises nickel or aluminum.
3. The method of claim 1 , wherein an n-type layer which is more heavily doped with an n-type dopant than the second layer of n-type SiC is between the second layer of n-type SiC and the layer of p-type SiC on the SiC substrate layer.
4. The method of claim 3 , wherein the SiC substrate is on a metal layer.
5. The method of claim 1 , wherein annealing occurs before depositing the one or more layers of dielectric material.
6. The method of claim 1 , further comprising etching the one or more dielectric layers after depositing the Schottky metal.
7. The method of claim 1 , further comprising depositing metal on the Schottky metal and on the ohmic contacts on the upper surfaces of the one or more raised regions.
8. The method of claim 1 , wherein depositing one or more layers of dielectric material comprises depositing a layer of SiO 2 on exposed surfaces of the first and second layers of n-type SiC.
9. The method of claim 1 , wherein depositing one or more layers of dielectric material comprises depositing a layer of Si 3 N 4 and subsequently depositing a layer of SiO 2 on exposed surfaces of the first and second layers of n-type SiC.
10. A semiconductor device made by the method of claim 1 .
11. The semiconductor device of claim 10 , wherein the plurality of discrete raised regions are elongate, having a major and a minor dimension, and wherein the major dimensions of the raised regions are oriented parallel to one another.
12. The semiconductor device of claim 11 , wherein the plurality of raised regions are spaced apart from one another at regular intervals in the direction of the minor dimension.
13. A semiconductor device made by the method of claim 2 .
14. A semiconductor device made by the method of claim 3 .
15. A semiconductor device made by the method of claim 9 .