Semiconductor wafer testing apparatus and method of testing semiconductor wafer

1. A method of testing a semiconductor wafer using a semiconductor chip test program stored in a storage unit of a semiconductor wafer testing apparatus, the method comprising:

selecting a predetermined number of semiconductor chips from among a plurality of semiconductor chips formed on a semiconductor wafer using said semiconductor wafer testing apparatus;

performing a first test on I/O pins of each of said selected semiconductor chips using said semiconductor wafer testing apparatus; and

performing a second test on a part of said I/O pins of each one of the non-selected semiconductor chips using said semiconductor wafer testing apparatus,

wherein said semiconductor wafer is divided into n regions, wherein n is a natural number more than 1, and said plurality semiconductor chips are formed in said n regions, said selecting comprises:

selecting m regions from said n regions, wherein m is a natural number smaller than n; and

selecting semiconductor chips from each of said selected m regions as said semiconductor chips of the predetermined number, and

said J semiconductor chips are in a range of 0.1 to 0.3% of said plurality of semiconductor chips.

2. The method according to claim 1 , wherein said performing a first test includes performing said first test of test items on said I/O pins of each of said selected semiconductor chips, and said performing a second test includes performing said second test of said test items on the I/O pins of each one of said non-selected semiconductor chips.

3. The method according to claim 1 , wherein said semiconductor wafer is divided into n regions, wherein n is a natural number more than 1, and said plurality semiconductor chips are formed in said n regions, said selecting comprises:

selecting m regions from said n regions, wherein m is a natural number smaller than n; and

selecting J semiconductor chips from said selected m regions, wherein J is a natural number.

4. A method of testing a semiconductor wafer using a semiconductor chip test program stored in a storage unit of a semiconductor wafer testing apparatus, comprising:

selecting a predetermined number of semiconductor chips from among a plurality of semiconductor chips formed on a semiconductor wafer using said semiconductor wafer testing apparatus;

performing a first test on I/O pins of each of said selected semiconductor chips using said semiconductor wafer testing apparatus;

performing a second test on a part of said I/O pins of each one of non-selected semiconductor chips using said semiconductor wafer testing apparatus; and

calculating a cumulative defect percentage for each of said test items of said first test using said semiconductor wafer testing apparatus,

wherein said performing a second test comprises performing said second test on the I/O pins for each one of said non-selected semiconductor chips when said cumulative defect percentage is not higher than a preset defect percentage, and

wherein said semiconductor wafer is divided into n regions, wherein n is a natural number more than 1, and said plurality semiconductor chips are formed in said n regions, said selecting comprises:

selecting m regions from said n regions, wherein m is a natural number smaller than n; and

selecting semiconductor chips from each of said selected m regions as said semiconductor chips of the predetermined number.

5. A semiconductor wafer testing apparatus which tests semiconductor chips formed in regions of a semiconductor wafer, comprising:

a CPU;

a storage unit configured to store a semiconductor chip test program; and

a communication unit configured to receive and hold a data signal sent from each of said semiconductor chips,

wherein said CPU reads out and executes said semiconductor chip test program from said storage unit, and

said CPU, based on said semiconductor chip test program:

selects semiconductor chips from a plurality of semiconductor chips formed in divided regions of said semiconductor wafer;

performs a first test of test items on each of said selected semiconductor chips;

performs a second test of necessary ones of the test items on each of non-selected semiconductor chips, said test items containing said necessary test items and selected test items;

compares a cumulative defect percentage of each of said selected test items with a preset defect percentage;

determines whether a third test of said selected test items should be performed on each of said non-selected semiconductor chips, based on the comparing result;

when said cumulative defect percentage of said selected test items is higher than said preset defect percentage, performs said third test of said test items on each of said non-selected semiconductor chips, and

when said cumulative defect percentage of said selected test items is not higher than said preset defect percentage, calculates a pin defect percentage for each of the I/O pins of each of said non-selected semiconductor chips; and

selects test omissible I/O pins of each of said non-selected semiconductor chips based on said defect percentage, performs said third test of said selected test items on a remaining I/O pin as at least one of said I/O pins other than said test omissible I/O pins in each of said non-selected semiconductor chips, and updates said cumulative defect percentage for each of said selected test items and for the remaining I/O pin.