Test mode control device using nonvolatile ferroelectric memory
View Patent ↗A test mode control device using a nonvolatile ferroelectric memory enables a precise test of characteristics of a memory cell array by changing a reference voltage and timing regulated for a memory cell test in a software system without extra processes. In an embodiment, test modes and arrangement of data pins are programmed using a nonvolatile ferroelectric memory, and addresses, control signals and arrangement of data pins are regulated in a software system depending on a programmed code. As a result, characteristics of a cell array can be precisely tested without extra processes.
1. A test mode control device using a nonvolatile ferroelectric memory, comprising:
a plurality of pads to receive a control signal and an address;
a plurality of buffers for buffering the control signal and the address inputted from the plurality of pads;
a pad register unit for programming a code for assignment of the control signal and the address inputted into the pad in a nonvolatile ferroelectric memory, and changing a connection path between the plurality of pads and the plurality of buffers depending on the programmed code; and
a path control means for controlling connection between the plurality of pads and the plurality of buffers in response to the register control signal.
2. The device according to claim 1 , wherein the path control means comprises:
a first path controller for connecting a control pad to a control buffer and an address pad to an address buffer in activation of a first register control signal; and
a second path controller for connecting the control pad to the address buffer and the address pad to the control buffer in activation of a second register control signal having an opposite phase to the first register control signal.
3. The device according to claim 2 , wherein the first path controller comprises:
a first switching device, connected between the control pad and the control buffer, to be switched by the first register control signal; and
a second switching device, connected between the address pad and the address buffer, to be switched by the first register control signal.
4. The device according to claim 2 , wherein the second path controller comprises:
a third switching device, connected between the address pad and the control buffer, to be switched by the second register control signal; and
a fourth switching device, connected between the control pad and the address buffer, to be switched by the second register control signal.
5. The device according to claim 1 , wherein the pad register unit comprises:
a program command processor for outputting a command signal to code a program command in response to a write enable signal, a chip enable signal, an output enable signal and a reset signal;
a program register controller for performing a logic operation on input data, a power-up detecting signal and the command signal, and outputting a write control signal and a cell plate signal;
a program register array comprising a nonvolatile ferroelectric memory device, for outputting the programmed code in response to a pull-up enable signal, a pull-down enable signal, the write control signal and the cell plate signal; and
a reset circuit unit for outputting the reset signal into the program register controller in a power-up mode.