Layout design apparatus, layout design method, and computer product

1. A layout design apparatus comprising:

a frame input unit that receives an input of a frame having a buffer tree that is clock-skew-adjusted embedded, the buffer tree including a root buffer serving as a start point and a plurality of branching buffers;

a netlist input unit that receives an input of a netlist concerning an input element for inputting a clock signal and an element to which the clock signal is supplied;

a placing unit that places the element and the input element in a placement area at an extremity of a buffer tree of the frame input by the frame input unit and on the frame, respectively, based on the netlist input by the netlist input unit;

a determining unit that determines a wiring route from the root buffer to the element in the buffer tree where the element is placed by the placing unit; and

a generating unit that generates a clock tree that starts at the input element and terminates at the elements placed in the placement area at the extremity of the buffer tree, based on the input element placed by the placing unit and the buffer tree having the wiring route determined by the determining unit.

2. The layout design apparatus according to claim 1 , further comprising a wiring unit that wires the input element placed by the placing unit and the root buffer, wherein

the generating unit generates the clock tree based on the input element and the root buffer wired by the wiring unit and the buffer tree having the wiring route determined by the determining unit.

3. The layout design apparatus according to claim 1 , further comprising a wiring unit that wires the input element placed by the placing unit and a distributing buffer from among the branching buffers, the distributing buffer distributes the clock signal to any one of the elements placed by the placing unit, wherein

the determining unit determines a wiring route from the distributing buffer to the element in the buffer tree, and

the generating unit generates a clock tree based on the input element and the distributing buffer wired by the wiring unit and the buffer tree having the wiring route determined by the determining unit.

4. The layout design apparatus according to claim 1 , wherein

the generating unit includes

an unused-line detecting unit that detects an unused line excluded from the wiring route determined by the determining unit; and

an eliminating unit that eliminates the unused line detected by the unused-line detecting unit, and

the generating unit generates the clock tree based on the buffer tree from which the unused line is eliminated.

5. The layout design apparatus according to claim 1 , wherein

the generating unit includes

an unused-line detecting unit that detects an unused line excluded from the wiring route determined by the determining unit; and

a replacing unit that replaces the branching buffer on the unused line detected by the unused-line detecting unit with a gate buffer capable of selectively permitting or inhibiting the propagation of the clock signal, and

the generating unit generates the clock tree based on the buffer tree having the gate buffer replaced by the replacing unit.

6. The layout design apparatus according to claim 1 , wherein

the netlist input unit receives an input of a plurality of netlists, and the generating unit generates the clock tree for each of the netlists so that the clock trees do not overlap each other.

7. A layout design method comprising:

receiving an input of a frame having a buffer tree that is clock-skew-adjusted embedded, the buffer tree including a root buffer serving as a start point and a plurality of branching buffers;

receiving an input of a netlist concerning an input element for inputting a clock signal and an element to which the clock signal is supplied;

placing the element and the input element in a placement area at an extremity of a buffer tree of the frame input by the frame input unit and on the frame, respectively, based on the netlist input by the netlist input unit;

determining a wiring route from the root buffer to the element in the buffer tree where the element is placed by the placing unit; and

generating a clock tree that starts at the input element and terminates at the elements placed in the placement area at the extremity of the buffer tree, based on the input element placed by the placing unit and the buffer tree having the wiring route determined by the determining unit.

8. A computer readable recording medium that stores a computer program for a layout design, the computer program making a computer execute:

receiving an input of a frame having a buffer tree that is clock-skew-adjusted embedded, the buffer tree including a root buffer serving as a start point and a plurality of branching buffers;

receiving an input of a netlist concerning an input element for inputting a clock signal and an element to which the clock signal is supplied;

placing the element and the input element in a placement area at an extremity of a buffer tree of the frame input by the frame input unit and on the frame, respectively, based on the netlist input by the netlist input unit;

determining a wiring route from the root buffer to the element in the buffer tree where the element is placed by the placing unit; and

generating a clock tree that starts at the input element and terminates at the elements placed in the placement area at the extremity of the buffer tree, based on the input element placed by the placing unit and the buffer tree having the wiring route determined by the determining unit.