IP Library Granted Patent US 7,552,414
Granted Patent B2
US 7,552,414 · App. 11/704,274 · Granted Jun 23, 2009

Layout design apparatus, layout design method, and computer product

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Quick Facts
Patent No.
US 7,552,414
App. No.
11/704,274
Granted
Jun 23, 2009
Kind
B2
Abstract

A frame input unit receives an input of a frame having a placement area for an element to which a predetermined signal is supplied. A netlist input unit receives an input of a netlist concerning the element. A placing unit places the element in the placement area of the frame input by the frame input unit based on the netlist input by the netlist input unit. A detecting unit detects whether there is a vacant position in the placement area in which the element is placed by the placing unit, and a bypass-element placing unit places a bypass element at the vacant position detected by the detecting unit, the bypass element propagating the predetermined signal by bypassing the element located adjacent to the vacant position.

Claims (18)

1. A layout design apparatus that communicates with a frame library and a netlist database, the apparatus comprising:

a frame input unit that receives, from the frame library, an input of a frame having a plurality of pre-placed elements to which a predetermined signal is supplied;

a netlist input unit that receives, from the netlist database, an input of a netlist concerning at least one of the plurality of pre-placed elements;

an assigning unit that assigns an element to which the predetermined signal is supplied in the netlist input by the netlist input unit to at least one of the plurality of pre-placed elements in the frame input by the frame input unit; and

an eliminating unit that eliminates a pre-placed element in the frame that is not assigned by the assigning unit.

2. The layout design apparatus according to claim 1 , wherein

the predetermined signal is a clock signal, and

the at least one pre-placed element and the element are phase-locked loop elements.

3. A layout design method for a layout design apparatus that communicates with a frame library and a netlist database, the method comprising:

receiving, from the frame library, an input of a frame having a plurality of pre-placed elements to which a predetermined signal is supplied;

receiving, from the netlist database, an input of a netlist concerning at least one of the plurality of pre-placed elements;

assigning an element to which the predetermined signal is supplied in the netlist input by the netlist input unit to at least one of the plurality of pre-placed elements in the frame input by the frame input unit; and

eliminating a pre-placed element in the frame that is not assigned by the assigning unit.

4. A computer readable recording medium that stores a computer program for a layout design, the computer program making a computer execute:

receiving an input of a frame having a plurality of pre-placed elements to which a predetermined signal is supplied;

receiving an input of a netlist concerning at least one of the plurality of pre-placed elements;

assigning an element to which the predetermined signal is supplied in the netlist input by the netlist input unit to at least one of the plurality of pre-placed elements in the frame input by the frame input unit; and

eliminating a pre-placed element in the frame that is not assigned by the assigning unit.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 27, 2015
From: FUJITSU SEMICONDUCTOR LIMITED
To: SOCIONEXT INC.
Reel/Frame 035508/0469 →
CHANGE OF NAME Recorded Jul 27, 2010
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 024794/0500 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 10, 2008
From: FUJITSU LIMITED
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 021985/0715 →