Voltage stress testing of core blocks and regulator transistors

1. A method comprising:

providing a circuit having an internal voltage regulator; and

disabling the internal voltage regulator to voltage stress test the circuit, wherein the internal voltage regulator comprises a regulator field-effect transistor (FET) and the circuit comprises an internal core block coupled to the regulator FET,

wherein disabling the internal voltage regulator comprises:

sensing a gate-to-source voltage (Vgs) of the regulator FET;

sensing a voltage applied to the internal core block;

comparing the voltage and the Vgs; and

controlling the Vgs of the regulator FET, based on the comparison of the voltage and the Vgs, to allow the voltage applied to the internal core block to be higher than a maximum voltage allowed by the internal voltage regulator.

2. The method of claim 1 , further comprising selecting at least one of a test mode of operation or a normal mode of operation, wherein disabling the internal voltage regulator of the circuit comprises disabling the internal voltage regulator while in the test mode.

3. The method of claim 1 , further comprising voltage stress testing the circuit.

4. The method of claim 3 , wherein voltage stress testing the circuit comprises voltage stress testing a gate oxide of the regulator FET.

5. The method of claim 3 , wherein voltage stress testing the circuit comprises voltage stress testing the internal core block.

6. The method of claim 5 , wherein voltage stress testing the internal core block comprises applying a voltage to the internal core block that is higher than a maximum voltage allowed by the internal voltage regulator.

7. An apparatus, comprising:

a circuit having an internal voltage regulator; and

a design-for-test (DFT) circuit coupled to the circuit to disable the internal voltage regulator to voltage stress test the circuit in a test mode, wherein the internal voltage regulator comprises a regulator field-effect transistor (FET), and wherein the circuit comprises an internal core block coupled to the regulator FET, wherein the DFT circuit comprises:

a first divider circuit coupled to sense a gate-to-source voltage (Vgs) of the regulator FET;

a second divider circuit to sense a voltage applied to the internal core block; and

a first comparator to compare an output of the first divider circuit and an output of the second divider circuit to control a voltage applied to the internal core block that is higher than a maximum voltage allowed by the internal voltage regulator.

8. The apparatus of claim 7 , wherein the DFT circuit further comprises a charge pump coupled to a gate of the regulator FET and coupled to receive an output of the first comparator, wherein the charge pump is configured to set the voltage of the gate of the regulator FET approximately equal to the voltage applied to the internal core block to allow the voltage applied to the internal core block to be higher than the maximum voltage allowed by the internal voltage regulator.

9. The apparatus of claim 7 ,

wherein the first divider circuit is configured to divide the Vgs by approximately 3.2 in a normal mode of operation and by approximately 3.8 in a test mode of operation;

wherein the second divider circuit is configured to divide the voltage by approximately 3.8 in both the normal mode of operation and the test mode of operation;

wherein the DFT circuit comprises:

a charge pump coupled to the regulator FET of the internal voltage regulator;

the first comparator to compare an output of the first divider circuit and an output of the second divider in the test mode of operation, and the output of the first divider circuit and a reference voltage in the normal mode of operation; and

a second comparator to compare the output of the second divider circuit and the reference voltage in the normal mode of operation, wherein the first and second comparators are configured to provide feedback to the charge pump to regulate the gate voltage of the regulator FET, wherein the regulator FET is configured to prevent the voltage applied to the internal core block to not be higher than a maximum voltage allowed by the internal voltage regulator in the normal mode of operation, and wherein the regulator FET is activated to allow the voltage applied to the internal core block to be higher than the maximum voltage allowed by the internal voltage regulator in the test mode of operation.

10. The apparatus of claim 7 , further comprising a microcontroller coupled to the DFT circuit to select at least one of the test mode of operation and a normal mode of operation.

11. The apparatus of claim 7 , wherein the DFT circuit is configured to voltage stress test the internal core block.

12. The apparatus of claim 7 , wherein the DFT circuit is configured to voltage stress test a gate oxide of the regulator FET.

13. The apparatus of claim 7 , wherein the apparatus has the test mode of operation and a normal mode of operation, wherein the DFT circuit in the test mode is configured to allow application of a voltage to the internal core block that is higher than a maximum voltage allowed by the internal voltage regulator of the circuit.