Metal-semiconductor field effect transistors (MESFETs) having self-aligned structures
Metal-semiconductor field-effect transistors (MESFETS) are provided. A MESFET is provided having a source region, a drain region and a gate. The gate is between the source region and the drain region. A p-type conductivity layer is provided beneath the source region, the p-type conductivity layer being self-aligned to the gate. Related methods of fabricating MESFETs are also provided herein.
1. A unit cell of a metal-semiconductor field-effect transistor (MESFET), comprising:
a MESFET having a first contact region, a second contact region and a gate, the gate being between the first contact region and the second contact region; and
a p-type conductivity layer beneath and spaced apart from the first contact region without extending to beneath the second contact region, the p-type conductivity layer being self-aligned to the gate.
2. The unit cell of claim 1 , further comprising:
a silicon carbide (SiC) substrate; and
a semiconductor layer on the SiC substrate, the semiconductor layer defining a recess and wherein the gate is provided in the recess.
3. The unit cell of claim 2 , wherein the gate has a length of from about 0.2 to about 0.4 μm.
4. The unit cell of claim 2 , wherein the gate comprises polysilicon.
5. The unit cell of claim 2 , further comprising a sidewall spacer on a sidewall of the gate.
6. The unit cell of claim 5 , wherein the first contact region comprises an n + region and wherein the n + region is self-aligned to the sidewall spacer on the sidewall of the gate.
7. The unit cell of claim 5 , wherein the sidewall spacer has a width of about 0.2 μm.
8. A unit cell of a metal-semiconductor field-effect transistor (MESFET), comprising:
a MESFET having a first contact region, a second contact region and a gate, the gate being between the first contact region and the second contact region;
a p-type conductivity layer beneath the first contact region, the p-type conductivity layer being self-aligned to the gate; and
an n-type conductivity layer beneath the first contact region that is self-aligned to the gate.
9. The unit cell of claim 1 , further comprising first and second contacts on the first and second contact regions, respectively.
10. The unit cell of claim 9 , further comprising a passivation layer on a surface of the MESFET including the first and second contacts, the passivation layer defining an opening that at least partially exposes a surface of the gate.
11. The unit cell of claim 10 , wherein a gate reinforcement metal is provided in the opening.
12. The unit cell of claim 11 , wherein the gate reinforcement metal has a width of from about 0.4 to about 0.6 μm.
13. A unit cell of a silicon carbide (SiC) metal-semiconductor field effect transistor (MESFET), comprising:
a SiC substrate;
a MESFET on the SiC substrate, the MESFET having a first contact region, a second contact region and a gate, the gate being between the first contact region and the second contact region;
a semiconductor layer on the SiC substrate that defines a recess, the gate being provided in the recess; and
a p-type conductivity layer beneath and spaced apart from the first contact region without extending to beneath the second contact region that is self-aligned to the gate.
14. The unit cell of claim 13 , wherein the gate has a length of from about 0.2 to about 0.4 μm.
15. The unit cell of claim 14 , wherein the gate comprises polysilicon.
16. The unit cell of claim 14 , further comprising a sidewall spacer on a sidewall of the gate in the recess.
17. The unit cell of claim 16 , wherein the first contact region comprises an n + region and wherein the n + region is self-aligned to the sidewall spacer on the sidewall of the gate.
18. The unit cell of claim 16 , wherein the sidewall spacer has a width of about 0.2 μm.
19. A unit cell of a silicon carbide (SiC) metal-semiconductor field effect transistor (MESFET), comprising:
a SiC substrate;
a MESFET on the SiC substrate, the MESFET having a first contact region, a second contact region and a gate, the gate being between the first contact region and the second contact region;
a semiconductor layer on the SIC substrate that defines a recess, the gate being provided in the recess;
a p-type conductivity layer beneath the first contact region that is self-aligned to the gate;
an n-type channel region between the SiC substrate and the semiconductor layer; and
a p + region in the n-type channel region that at least partially contacts the p-type conductivity region.
20. A unit cell of a silicon carbide (SiC) metal-semiconductor field effect transistor (MESFET), comprising:
a SiC substrate;
a MESFET on the SiC substrate, the MESFET having a first contact region, a second contact region and a gate, the gate being between the first contact region and the second contact region;
a semiconductor layer on the SiC substrate that defines a recess, the gate being provided in the recess;
a p-type conductivity layer beneath the first contact region that is self-aligned to the gate; and
an n-type conductivity layer beneath the first contact region that is self-aligned to the gate.
21. The unit cell of claim 13 , further comprising first and second contacts on the first and second contact regions, respectively.
22. The unit cell of claim 21 , further comprising a passivation layer on a surface of the MESFET including the first and second contacts, the passivation layer defining an opening that at least partially exposes a surface of the gate.
23. The unit cell of claim 22 , wherein a gate reinforcement metal is provided in the opening.
24. The unit cell of claim 23 , wherein the gate reinforcement metal has a width of from about 0.4 to about 0.6 μm.
25. A unit cell of a transistor comprising:
a transistor having a first contact region, a second contact region and a gate, the gate being between the first contact region and the second contact region; and
a conductivity layer beneath and spaced apart from the first contact region without extending to beneath the second contact region, the conductivity layer being substantially self-aligned to the gate.
26. The unit cell of claim 25 , further comprising:
a silicon carbide (SiC) substrate; and
a semiconductor layer on the SiC substrate, the semiconductor layer defining a recess and wherein the gate is provided in the recess.
27. The unit cell of claim 26 , wherein the gate has a length of from about 0.2 to about 0.4 μm.
28. The unit cell of claim 26 , wherein the gate comprises polysilicon.
29. The unit cell of claim 26 , further comprising a sidewall spacer on a sidewall of the gate.
30. The unit cell of claim 26 , wherein the first contact region comprises an n + region and wherein the n + region is self-aligned to the sidewall spacer on the sidewall of the gate.
31. The unit cell of claim 29 , wherein the sidewall spacer has a width of about 0.2 μm.
32. A unit cell of a transistor comprising:
a transistor having a first contact region, a second contact region and a gate, the gate being between the first contact region and the second contact region; and
a conductivity layer beneath the first contact region, the conductivity layer being substantially self-aligned to the gate,
wherein the conductivity layer comprises a p-type conductivity layer, the unit cell further comprising an n-type conductivity layer beneath the first contact region that is substantially self-aligned to the gate.
33. The unit cell of claim 25 , further comprising first and second contacts on the first and second contact regions, respectively.
34. The unit cell of claim 33 , further comprising a passivation layer on a surface of the transistor including the first and second contacts, the passivation layer defining an opening that at least partially exposes a surface of the gate.
35. The unit cell of claim 34 , wherein a gate reinforcement metal is provided in the opening.
36. The unit cell of claim 35 , wherein the gate reinforcement metal has a width of from about 0.4 to about 0.6 μm.