Semiconductor device having variable parameter selection based on temperature and test method
View Patent ↗The temperature sensing circuits may be used to control various parameters, such as internal regulated supply voltages, internal refresh frequency, a word line low voltage, or the like. In this way, operating specifications of a semiconductor device at worst case temperatures may be met without comprising performance at normal operating temperatures. Each temperature sensing circuit may include a selectable temperature threshold value as well as a selectable temperature hysteresis value. In this way, temperature performance characteristics may be finely tuned. Furthermore, a method of testing the temperature sensing circuits is disclosed in which a current value may be monitored and temperature threshold values and temperature hysteresis values may be thereby determined.
1. A dynamic random access memory device, comprising:
a self refresh mode having a first refresh frequency at a first temperature and a second refresh frequency at a second temperature wherein
the second temperature is greater than the first temperature and the second refresh frequency is greater than the first refresh frequency and the self refresh mode has a third refresh frequency lower than the first refresh frequency at a third temperature between the first temperature and the second temperature.
2. The dynamic random access memory device of claim 1 , wherein:
the refresh frequency of the self refresh mode decreases between the first temperature and the second temperature.
3. The dynamic random access memory device of claim 1 , further including:
a first temperature sensing circuit including a first temperature threshold value and providing a first temperature indication signal, the first temperature indication signal has a first logic level when the dynamic random access memory is at a temperature below the first temperature threshold value and a second logic level when the dynamic random access memory is at a temperature above the first temperature threshold value; and
a refresh circuit coupled to receive the first temperature indication signal.
4. The dynamic random access memory device of claim 1 , further including:
the first temperature sensing circuit includes a first temperature hysteresis value.
5. The dynamic random access memory device of claim 3 , wherein:
the first temperature threshold values is essentially the second temperature.
6. The dynamic random access memory device of claim 3 , wherein:
the first temperature threshold value is programmable.
7. The dynamic random access memory device of claim 3 , wherein:
a second temperature sensing circuit including a second temperature threshold value and providing a second temperature indication signal, the second temperature indication signal has the first logic level when the dynamic random access memory is at a temperature below the second temperature threshold value and the second logic level when the dynamic random access memory is at a temperature above the second temperature threshold value; and
a refresh circuit coupled to receive the second temperature indication signal.
8. The dynamic random access memory device of claim 3 , wherein:
the refresh circuit includes a counter circuit coupled to receive the first temperature indication signal.
9. The dynamic random access memory device of claim 3 , wherein:
the refresh circuit includes an oscillator circuit coupled to receive the first temperature indication signal.
10. The dynamic random access memory device of claim 3 , wherein:
the first temperature sensing circuit further includes a latch circuit coupled to receive the first temperature indication signal.
11. The dynamic random access memory device of claim 3 , wherein:
the first temperature sensing circuit is coupled to receive a temperature sensing enable signal having a temperature sensing disable logic level and a temperature sensing enable logic level.
12. The dynamic random access memory device of claim 4 , wherein:
the first temperature hysteresis value is programmable.
13. The dynamic random access memory device of claim 7 , wherein:
the second temperature threshold value is essentially the first temperature.
14. The dynamic random access memory device of claim 7 , wherein:
the second temperature threshold value is programmable.
15. The dynamic random access memory device of claim 7 , wherein:
the second temperature sensing circuit includes a first temperature hysteresis value.
16. The dynamic random access memory device of claim 15 , wherein:
the second temperature hysteresis value is programmable.
17. The dynamic random access memory device of claim 8 , wherein:
the counter circuit has a first predetermined count value when the first temperature indication signal has the first logic level and a second predetermined count value when the temperature indication signal has the second logic level.
18. The dynamic random access memory device of claim 17 , wherein:
the first predetermined count value is greater than the second predetermined count value.
19. The dynamic random access memory device of claim 9 , further including:
the oscillator circuit has a first predetermined frequency when the first temperature indication signal has the first logic level and a second predetermined frequency when the temperature indication signal has the second logic level.
20. The dynamic random access memory device of claim 19 , further including:
the first predetermined frequency is less than the second predetermined frequency.