IP Library Granted Patent US 8,008,130
Granted Patent B2
US 8,008,130 · App. 11/727,025 · Granted Aug 30, 2011

Multilayer interconnection board, semiconductor device having the same, and method of forming the same as well as method of mounting the semicondutor chip on the interconnection board

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,008,130
App. No.
11/727,025
Granted
Aug 30, 2011
Kind
B2
Abstract

In accordance with the present invention, during formation of the interconnection board, the interconnection board remains securely fixed to a high rigidity plate being higher in rigidity than the interconnection board for suppressing the interconnection board from being bent.

Claims (45)

1. A method of forming an interconnection board, comprising:

forming an interconnection board on a plate; and

removing said plate from a first side of said interconnection board thereby exposing at least one external electrode pad having an exposed surface level with said first side so that said first side and said exposed surface form a single flat plane;

forming a supporting plate having a plurality of holes corresponding to the exposed at least one external electrode pad of said interconnection board, into which a plurality of external electrodes are inserted, so that said supporting plate extends in parallel to a second surface of a buffer layer to form an inter-space between said supporting plate and said second surface of said buffer layer; and

forming a supporting sealing resin material which fills said inter-space and surrounding parts of said external electrodes so that said supporting sealing resin material is in contact with said parts of said external electrodes for supporting said external electrodes,

wherein during the forming of said interconnection board, said interconnection board remains fixed to said plate, and during the removing said plate the exposed surface of said at least one external electrode pad remains exposed.

2. The method as claimed in claim 1 , wherein said interconnection board comprises a multilayer interconnection board having a multilevel interconnection structure.

3. The method as claimed in claim 1 , the removing said plate includes completely removing said plate from said interconnection board, after said interconnection board is fabricated on said plate.

4. The method as claimed in claim 3 , wherein said plate is made of a metal.

5. The method as claimed in claim 3 , wherein said plate is made of an alloy.

6. The method as claimed in claim 3 , wherein said high rigidity plate is made of a ceramic.

7. The method as claimed in claim 3 , wherein said interconnection board includes an organic insulative material.

8. The method as claimed in claim 7 , wherein said organic material is a polymer resin material.

9. The method as claimed in claim 1 , further comprising the step of: selectively removing said high rigidity plate from said interconnection board to form plural generally column shaped electrically conductive layers on said interconnection board, after said interconnection board is fabricated on said high rigidity plate.

10. The method as claimed in claim 9 , further comprising the step of: forming external electrodes on said plural generally column shaped electrically conductive layers so that said external electrodes are electrically connected through said plural generally column shaped electrically conductive layers to said interconnection board.

11. The method as claimed in claim 9 , further comprising the step of: forming an stress absorption layer being lower in rigidity than said plural generally column shaped electrically conductive layers, which fills gaps between said plural generally column shaped electrically conductive layers, so that said stress absorption layer surrounds said plural generally column shaped electrically conductive layers, whereby said stress absorption layer is in tightly contact with said plural generally column shaped electrically conductive layers.

12. The method as claimed in claim 11 , further comprising the step of: forming external electrodes on said plural generally column shaped electrically conductive layers so that said external electrodes are electrically connected through said plural generally column shaped electrically conductive layers to said interconnection board.

13. The method as claimed in claim 12 , further comprising the step of:

forming a supporting plate having plural holes, into which said external electrodes are inserted, so that said supporting plate extends in parallel to said second surface of said buffer layer to form an inter-space between said supporting plate and said second surface of said buffer layer; and

forming a supporting sealing resin material which fills said inter-space and surrounding parts of said external electrodes so that said supporting sealing resin material is in tightly contact with said parts of said external electrodes for supporting said external electrodes.

14. The method as claimed in claim 1 , further comprising the step of:

bonding a plurality of column-shaped electrically conductive layers to said exposed at least one external electrode pad of said interconnection board via an adhesive; and

forming external electrodes on said plurality of column-shaped electrically conductive layers so that said external electrodes are electrically connected through said plurality of column-shaped electrically conductive layers to said exposed at least one external electrode pad of said interconnection board.

15. A method of forming an interconnection board, comprising:

forming an interconnection board on a plate; and

removing said plate from a first side of said interconnection board thereby exposing at least one external electrode pad having an exposed surface level with said first side so that said first side and said exposed surface form a single flat plane;

bonding a plurality of column-shaped electrically conductive layers to said exposed at least one external electrode pad of said interconnection board via an adhesive;

forming external electrodes on said plurality of column-shaped electrically conductive layers so that said external electrodes are electrically connected through said plurality of column-shaped electrically conductive layers to said exposed at least one external electrode pad of said interconnection board;

forming a supporting plate having a plurality of holes corresponding to said exposed at least one external electrode pad of said interconnection board, into which said plurality of column-shaped electrically conductive layers with said external electrodes are inserted, and said supporting plate extending in parallel to a second surface of said interconnection board to form an inter-space between said supporting plate and said second surface of said interconnection board; and

forming a supporting sealing resin material which fills said inter-space and surrounds both said plurality of column-shaped electrically conductive layers and parts of said external electrodes so that said supporting sealing resin material is in contact with said plurality of column-shaped electrically conductive layers and said parts of said external electrodes for supporting said external electrodes;

wherein during the forming of said interconnection board, said interconnection board remains fixed to said plate, and during the removing said plate the exposed surface of said at least one external electrode pad remains exposed.

16. The method as claimed in claim 1 , further comprising the step of:

mounting at least a semiconductor chip on said interconnection board; and

completely removing said plate from said interconnection board.

17. The method as claimed in claim 1 , further comprising the step of:

mounting at least a semiconductor chip on said interconnection board;

forming at least a heat spreader on said at least semiconductor chip; and

completely removing said plate from said interconnection board.

18. The method as claimed in claim 1 further comprising the step of:

mounting at least a semiconductor chip on said interconnection board; and

selectively removing said high rigidity plate from said interconnection board to form plural generally column shaped electrically conductive layers on said interconnection board.

19. The method as claimed in claim 1 further comprising the step of:

mounting at least a semiconductor chip on said interconnection board;

forming at least a heat spreader on said at least semiconductor chip; and

selectively removing said high rigidity plate from said interconnection board to form plural generally column shaped electrically conductive layers on said interconnection board.

Assignments (2)
CHANGE OF NAME Recorded Nov 4, 2010
From: NEC ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 025311/0860 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 23, 2007
From: NEC CORPORATION
To: NEC ELECTRONICS CORPORATION
Reel/Frame 019165/0340 →