Semiconductor integrated circuit device and delay fault testing method

1. A semiconductor integrated circuit device comprising:

a plurality of flip-flops configured to form a scan chain in a scan path test to operate as a shift register;

wherein a first flip-flop of said plurality of flip-flops latches a first input signal in synchronization with a clock signal, outputs a first output signal and fixes a signal level of the first output signal regardless of changing a signal level of a first signal flowing in a first signal route from an output of a third flip-flop of said plurality of flip-flops to an input of said first flip-flop based on a first selection control signal;

wherein a second flip-flop of said plurality of flip-flops latches a second input signal in synchronization with the clock signal, outputs a second output signal, and fixes a signal level of the second output signal regardless of changing a signal level of a second signal flowing in a second signal route from an output of a fourth flip-flop of said plurality of flip-flops to an input of said second flip-flop, based on a second selection control signal; and

a control circuit configured to generate the first and second selection control signals such that a period during which said first flip-flop fixes the signal level of the first output signal is different from a period during which said second flip-flop fixes the signal level of the second output signal.

2. A semiconductor integrated circuit device comprising:

a plurality of flip-flops configured to form a scan chain in a scan path test to operate as a shift register;

wherein a first flip-flop of said plurality of flip-flops latches a first input signal in synchronization with a clock signal, outputs a first output signal and fixes the first output signal based on the first selection control signal;

wherein a second flip-flop of said plurality of flip-flops latches a second input signal in synchronization with the clock signal, outputs a second output signal, and fixes the second output signal based on a second selection control signal;

a control circuit configured to generate the first and second selection control signals such that a period during which said first flip-flop fixes the first output signal is different from a period during which said second flip-flop fixes the second output signal;

a first selecting circuit configured to select one of the first output signal and a first combination signal outputted from a combination circuit based on the first selection control signal and to output the selected signal to said first flip-flop as the first input signal; and

a second selecting circuit configured to select one of the second output signal and a second combination signal outputted from said combination circuit based on the second selection control signal and to output the selected signal to said second flip-flop as the second input signal.

3. The semiconductor integrated circuit device according to claim 2 , wherein a signal route from an output of said first flip-flop to an input of said second flip-flop is a timing exception path which is not necessary for a delay time to fall within a one clock cycle of the clock signal.

4. The semiconductor integrated circuit device according to claim 2 , wherein said control circuit generates the first and second selection control signals based on a test execution signal indicating that a delay fault test is executed to detect a delay fault.

5. The semiconductor integrated circuit device according to claim 2 , wherein said control circuit determines whether said first flip-flop inputs the first output signal or said second flip-flop inputs the second output signal, based on an external hold control signal, and generates the first and second selection control signal.

6. The semiconductor integrated circuit device according to claim 5 , wherein said scan chain of said plurality of flip-flops comprises a third flip-flop configured to output the hold control signal.

7. The semiconductor integrated circuit device according to claim 6 , wherein a test data supplied to said scan chain is set in said third flip-flop and contains a data showing the hold control signal.

8. A delay fault test method comprising:

forming a scan chain from a plurality of flip-flops in a scan path test to operate as a shift register;

holding a first output signal of a first flip-flop of said plurality of flip-flops in response to a first selection control signal;

holding a second output signal of a second flip-flop of said plurality of flip-flops in response to a second selection control signal; and

generating the first and second selection control signals such that a period during which said first flip-flop fixes the first output signal is different from a period during which said second flip-flop fixes the second output signal,

wherein a delay fault is tested by supplying a test data to said scan chain.

9. The delay fault test method according to claim 8 , wherein said plurality of flip-flops operate in synchronization with a clock signal,

said delay fault test method further comprises:

setting a start point flip-flop of a timing exception path in a signal route set to said plurality of flip-flops to said first flip-flop;

wherein the timing exception path is not necessary for a delay time when a signal is transferred on said signal route to fall within one clock cycle of the clock signal; and

setting an end point flip-flop of the timing exception path to said second flip-flop.

10. The delay fault test method according to claim 8 , wherein said generating the first and second selection control signals comprises:

generating the first and second selection control signals based on a test execution signal indicating that a delay fault test is executed to detect a delay fault.

11. The delay fault test method according to claim 8 , wherein said generating the first and second selection control signals comprises:

validating the first selection control signal or the second selection control signal based on a hold control signal.

12. The delay fault test method according to claim 8 , wherein said generating the first and second selection control signals comprises:

validating the first selection control signal or the second selection control signal based on the test data.