MOS transistor and method for producing a MOS transistor structure
View Patent ↗A MOS transistor, and a method for producing the same, is provided with a source region, a gate-region, a drain region, and a drift region in an SOI wafer. The SOI-wafer has a carrier layer, which carries an insulating intermediate layer, and whereby the insulating intermediate layer carries an active semiconductor layer, in which laterally different doping material concentrations define the source region, the drift region, and the drain region. Whereby, the active semiconductor layer, at least in a portion of the drift region, is thicker than in the source region. The MOS transistor is characterized in that the active semiconductor layer, in a vertical direction, is completely separated by the insulating intermediate layer from the carrier layer.
1. A method for producing a MOS transistor structure having a source region, a gate-region, a drain region, and a drift region in an SOI wafer, the SOI wafer having a carrier layer, which carries an insulating intermediate layer, the insulating intermediate layer carrying an active semiconductor layer, in which laterally different doping material concentrations define the source region, the drift region, and the drain-region, the active semiconductor layer at least in a portion of the drift region is thicker than in the source region, the method steps comprising:
producing a trench in an SOI wafer, which serves as a starting material with an active layer having a first thickness, the trench cutting through an initially planar insulating intermediate layer, the insulating intermediate layer being applied to walls and a bottom of the trench;
removing the insulating intermediate layer at least in a region from the walls, which cut through the active layer; and
filling the trench with an active semiconductor layer, which is thicker than the active semiconductor layer in the source region, to form the portion of the drift region.
2. The method according to claim 1 , wherein the filling of the trench occurs by a selective epitaxial lateral overgrowth.
3. The method according to claim 2 , wherein portions of the walls of the trench, which cut through the active layer, function as seed openings for the selective epitaxial overgrowth.
4. The method according to claim 2 , wherein the entire trench is filled by the epitaxial growth and that epitaxial mushrooms formed during the growth are removed by chemical/mechanical polishing such that a largely planar surface of the MOS transistor structure results.
5. The method according to claim 2 , wherein doping is changed during the selective epitaxy.
6. A method for producing a MOS transistor structure comprising:
providing an SOI wafer comprising a carrier layer, an insulating intermediate layer on the carrier layer and an active semiconductor layer on the insulating intermediate layer;
forming a trench in the SOI wafer extending through the active semiconductor layer and the intermediate insulating layer and into the carrier layer, the trench including at least one sidewall and a bottom;
applying an insulator material to at least a portion of the at least one sidewall and bottom of the trench;
filling the trench with an active semiconductor material such that the thickness of the active semiconductor material in the trench is greater than the thickness of the active semiconductor layer; and
forming a source region a gate region, a drain region and a drift region in the active semiconductor layer, the active semiconductor material in the trench forming a part of the drift region.
7. The method of claim 6 including removing the insulator material from a portion of the trench at least one sidewall that extends through the active semiconductor layer.
8. The method of claim 6 wherein filling the trench comprises filling the trench by selective epitaxial lateral overgrowth.
9. The method of claim 8 , including using portions of the walls of the trench in the active semiconductor layer as seed openings for the selective epitaxial lateral overgrowth.
10. The method of claim 8 wherein filling the trench comprises filling the trench until an epitaxial mushroom is formed and removing the epitaxial mushroom by chemical/mechanical polishing to produce a generally planar surface over the trench.
11. The method of claim 8 , including varying a doping level during the selective epitaxial lateral overgrowth.
12. The method of claim 6 , wherein forming the drift region in the active semiconductor layer comprises forming the drift region in the active semiconductor layer and in the active semiconductor material.
13. The method of claim 6 wherein the insulating layer is formed of the insulator material.
14. The method of claim 6 wherein the active semiconductor layer is formed of the semiconductor material.