Tester input/output sharing
View Patent ↗In one implementation, a method of testing multiple DUTs using a single tester channel is provided which includes providing an input signal with the single tester channel simultaneously to each of the DUTs. The method further includes providing a clock signal to each of the DUTs. The clock signal provided to each of the DUTs may be successively delayed clock signals, which are provided to successive DUTs. The method includes using the clock signal to cause a next DUTs to provide an output transition before an output of a prior DUT is returned to a pre-transition state. The method further includes detecting with the single tester channel the output transition of each of the DUTs in response to the input signal and the clock signal.
1. A method of testing in an automated tester, the method comprising:
testing a plurality of devices under test using a single tester channel comprising:
providing an input signal simultaneously to each of the plurality of devices under test using the single tester channel;
providing successively delayed clock signals to successive devices under test;
detecting with the single tester channel a cumulative output from the plurality of devices under test using the single tester channel; and
based on the cumulative output determining, for each of the plurality of devices under test, a response of the device under test to the input signal.
2. The method of claim 1 , wherein providing the input signal simultaneously to each of a plurality of devices under test comprises using a series-to-parallel connection on a device interface board to connect the single tester channel to the plurality of devices under test.
3. The method of claim 2 , wherein providing the input signal simultaneously to each of a plurality of devices under test further comprises providing a switch connected between the series-to-parallel connection and each of the plurality of devices under test.
4. The method of claim 1 , wherein providing the input signal simultaneously to each of a plurality of devices under test further comprises providing a series-to-parallel connection prior to a device interface board to connect the single tester channel to the plurality of devices under test.
5. The method of claim 4 , wherein providing the input signal simultaneously to each of a plurality of devices under test further comprising providing a resistor between the series-to-parallel connection and each of the plurality of devices under test.
6. The method of claim 5 , wherein providing the input signal simultaneously to each of a plurality of devices under test further comprising providing a switch between the series-to-parallel connection and each of the plurality of devices under test.
7. The method of claim 1 , wherein the successively delayed clock signals have relative delays causing a next device under test to provide an output transition before an output of a prior device under test is returned to a pre-transition state.
8. The method of claim 1 , wherein testing the plurality of devices under test using the single tester channel further comprises providing series connections to connect the plurality of devices under test.
9. An automated tester comprising:
a) a test channel comprising a bi-directional input and output circuit;
b) a series to parallel circuit configured so as to be capable of connecting the bi-directional input and output circuit to a plurality of devices under test;
c) a plurality of clock circuits each configured so as to be capable of being connected to a respective one of the plurality of devices under test; and
d) wherein the tester is configured to perform bi-directional testing of the plurality of devices under test with the test channel by:
providing an input signal with the test channel simultaneously to each of a plurality of devices under test;
causing a next device under test to provide an output transition before an output of a prior device under test is returned to a pre-transition state using successively delayed clock signals provided to successive devices under test;
measuring a cumulative response output of the plurality of devices under test; and
based on the cumulative response output, for each of the plurality of devices under test, determining a response of the device under test to the input signal.
10. The automated tester of claim 9 , wherein the tester further comprises a device interface board adapted to hold the plurality of devices under test, and wherein the series-to-parallel connection is located on the device interface board.
11. The automated tester of claim 10 further comprising a resistor connected between the series-to-parallel connection and each of the plurality of devices under test.
12. The automated tester of claim 11 further comprising a switch connected between the series-to-parallel connection and each of the plurality of devices under test.
13. The automated tester of claim 9 , wherein the tester further comprises a device interface board adapted to hold the plurality of devices under test, and wherein the series-to-parallel connection is located between the bi-directional input and output circuit and the device interface board.
14. The automated tester of claim 13 , wherein the tester further comprises a switch between the series-to-parallel connection and each of the plurality of devices under test.
15. The automated tester of claim 14 further comprising a resistor connected between the series-to-parallel connection and each of the plurality of devices under test.
16. The automated tester of claim 9 , wherein the output of the devices under test are connected in series with each other and in series with the test channel.
17. A method of testing in an automated tester, the method comprising:
testing a plurality of devices under test using a single tester channel comprising:
providing an input signal with the single tester channel simultaneously to each of a plurality of devices under test;
providing a clock signal to each of the plurality of devices under test;
using the clock signal to cause a next device under test to provide an output transition before an output of a prior device under test is returned to a pre-transition state; and
detecting with the single tester channel a cumulative response output representing the output transition of each of the plurality of devices under test in response to the input signal and the clock signal.
18. The method of claim 17 , wherein providing the clock signal to each of the plurality of devices under test comprises providing successively delayed clock signals to successive devices under test.
19. The method of claim 17 , wherein detecting comprises measuring a cumulative response.
20. The method of claim 17 , wherein detecting comprises detecting an incremental change in a cumulative output of the plurality of devices under test.
21. The method of claim 17 , wherein providing an input signal with the single tester channel simultaneously to each of a plurality of devices under test comprises using a series-to-parallel connection on a device interface board to connect the single tester channel to the plurality of devices under test.
22. The method of claim 21 , wherein providing an input signal with the single tester channel simultaneously to each of a plurality of devices under test further comprises providing a switch connected between the series-to-parallel connection and each of the plurality of devices under test.
23. The method of claim 17 , wherein providing an input signal with the single tester channel simultaneously to each of a plurality of devices under test further comprises providing a series-to-parallel connection in a test head to connect the single tester channel to the plurality of devices under test.
24. The method of claim 23 , wherein providing an input signal with the single tester channel simultaneously to each of a plurality of devices under test further comprising providing a switch between the series-to-parallel connection and each of the plurality of devices under test.
25. The method of claim 17 , wherein testing the plurality of devices under test using the single tester channel further comprises providing series connections between the plurality of devices under test.
26. An automated tester comprising:
a) a test channel comprising a bi-directional input and output circuit;
b) a series to parallel circuit configured so as to be capable of connecting the bi-directional input and output circuit to a plurality of devices under test;
c) a plurality of clock circuits each configured so as to be capable of being connected to a respective one of the plurality of devices under test; and
d) the tester being configured to perform bi-directional testing of the plurality of devices under test with the test channel by:
providing an input signal with the test channel simultaneously to each of a plurality of devices under test;
causing a next device under test to provide an output transition before an output of a prior device under test is returned to a pre-transition state; and
detecting with the test channel a cumulative response signal comprising the output transition of each of the plurality of devices under test in response to the input signal and the clock signal.
27. The automated tester of claim 26 , wherein the tester is adapted so as to provide successively delayed clock signals to successive devices under test.
28. The automated tester of claim 26 , wherein the tester is adapted so as to measure a cumulative response output of the plurality of devices under test.
29. The automated tester of claim 26 , wherein the tester is adapted so as to detect an incremental change in a cumulative response output of the plurality of devices under test.
30. The automated tester of claim 26 , wherein the tester is adapted so as to detect a rate of change of the output.
31. The automated tester of claim 26 , wherein the tester further comprises a device interface board adapted to hold the plurality of devices under test, and wherein the series-to-parallel connection is located on the device interface board.
32. The automated tester of claim 31 , wherein the tester further comprises a resistor between the series-to-parallel connection and each of the plurality of devices under test.
33. The automated tester of claim 26 , wherein the tester further comprises a device interface board adapted to hold the plurality of devices under test, and wherein the series-to-parallel connection is located between the bi-directional input and output circuit and the device interface board.
34. The automated tester of claim 33 , wherein the tester further comprises a resistor between the series-to-parallel connection and each of the plurality of devices under test.
35. The automated tester of claim 34 , wherein the tester further comprises a switch between the series-to-parallel connection and each of the plurality of devices under test.
36. The automated tester of claim 26 , wherein the output of the devices under test are connected in series with each other and in series with the test channel.